1 /*
2 * Copyright (c) 2006-2023, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Email: opensource_embedded@phytium.com.cn
7 *
8 * Change Logs:
9 * Date Author Notes
10 * 2023/7/24 liqiaozhong first add, support intr
11 * 2024/6/3 zhangyan Adaptive drive
12 *
13 */
14
15 #include "rtconfig.h"
16 #include <rtthread.h>
17 #include <rtdevice.h>
18 #include "interrupt.h"
19 #define LOG_TAG "gpio_drv"
20 #include "drv_log.h"
21 #ifdef RT_USING_SMART
22 #include "ioremap.h"
23 #endif
24
25 #include "fparameters.h"
26 #include "fkernel.h"
27 #include "fcpu_info.h"
28 #include "ftypes.h"
29 #include "fio_mux.h"
30 #include "board.h"
31
32 #include "fiopad.h"
33 #include "fgpio.h"
34 #include "drv_gpio.h"
35 /**************************** Type Definitions *******************************/
36
37 /***************** Macros (Inline Functions) Definitions *********************/
38
39 /************************** Variable Definitions *****************************/
40 static FGpio gpio_device[FGPIO_PIN_NUM * FGPIO_PORT_NUM * FGPIO_CTRL_NUM + 1];
41 extern FGpioIntrMap fgpio_intr_map[FGPIO_CTRL_NUM];
42 /*******************************Api Functions*********************************/
FGpioOpsSetupIRQ(FGpio * ctrl)43 static void FGpioOpsSetupIRQ(FGpio *ctrl)
44 {
45 rt_uint32_t cpu_id = rt_hw_cpu_id();
46 u32 irq_num = ctrl->config.irq_num;
47
48 LOG_D("In FGpioOpsSetupIRQ() -> cpu_id %d, irq_num %d\r\n", cpu_id, irq_num);
49 rt_hw_interrupt_set_target_cpus(irq_num, cpu_id);
50 rt_hw_interrupt_set_priority(irq_num, 0xd0); /* setup interrupt */
51 rt_hw_interrupt_install(irq_num, FGpioInterruptHandler, NULL, NULL); /* register intr handler */
52 rt_hw_interrupt_umask(irq_num);
53
54 return;
55 }
56
57 /* on E2000, if u want use GPIO-4-11, set pin = FGPIO_ID(4, 11) */
drv_pin_mode(struct rt_device * device,rt_base_t pin,rt_uint8_t mode)58 static void drv_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode)
59 {
60 FGpio *instance = (FGpio *)device->user_data;
61 FError err = FGPIO_SUCCESS;
62 u32 index = (u32)pin;
63
64 FGpioConfig input_cfg = *FGpioLookupConfig(index);
65 rt_memset(&instance[index], 0, sizeof(FGpio));
66 #ifdef RT_USING_SMART
67 input_cfg.base_addr = (uintptr)rt_ioremap((void *)input_cfg.base_addr, 0x1000);
68 #endif
69 err = FGpioCfgInitialize(&instance[index], &input_cfg);
70 if (FGPIO_SUCCESS != err)
71 {
72 LOG_E("Ctrl: %d init fail!!!\n");
73 }
74
75 FIOPadSetGpioMux(instance[index].config.ctrl, instance[index].config.pin);
76
77 switch (mode)
78 {
79 case PIN_MODE_OUTPUT:
80 FGpioSetDirection(&instance[index], FGPIO_DIR_OUTPUT);
81 break;
82 case PIN_MODE_INPUT:
83 FGpioSetDirection(&instance[index], FGPIO_DIR_INPUT);
84 break;
85 default:
86 rt_kprintf("Not support mode %d!!!\n", mode);
87 break;
88 }
89 }
90
drv_pin_write(struct rt_device * device,rt_base_t pin,rt_uint8_t value)91 void drv_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value)
92 {
93 FGpio *instance = (FGpio *)device->user_data;
94 u32 index = (u32)pin;
95
96 FGpioSetOutputValue(&instance[index], (value == PIN_HIGH) ? FGPIO_PIN_HIGH : FGPIO_PIN_LOW);
97 }
98
drv_pin_read(struct rt_device * device,rt_base_t pin)99 rt_ssize_t drv_pin_read(struct rt_device *device, rt_base_t pin)
100 {
101 FGpio *instance = (FGpio *)device->user_data;
102 u32 index = (u32)pin;
103
104 return FGpioGetInputValue(&instance[index]) == FGPIO_PIN_HIGH ? PIN_HIGH : PIN_LOW;
105 }
106
drv_pin_attach_irq(struct rt_device * device,rt_base_t pin,rt_uint8_t mode,void (* hdr)(void * args),void * args)107 rt_err_t drv_pin_attach_irq(struct rt_device *device, rt_base_t pin,
108 rt_uint8_t mode, void (*hdr)(void *args), void *args)
109 {
110 FGpio *instance = (FGpio *)device->user_data;
111 u32 index = (u32)pin;
112 rt_base_t level;
113
114 #ifdef RT_USING_SMART
115 FGpioIntrMap *map = &fgpio_intr_map[instance[index].config.ctrl];
116 map->base_addr = (uintptr)rt_ioremap((void *)map->base_addr, 0x1000);
117 #endif
118
119 level = rt_hw_interrupt_disable();
120
121 FGpioOpsSetupIRQ(&instance[index]);
122
123 switch (mode)
124 {
125 case PIN_IRQ_MODE_RISING:
126 FGpioSetInterruptType(&instance[index], FGPIO_IRQ_TYPE_EDGE_RISING);
127 break;
128 case PIN_IRQ_MODE_FALLING:
129 FGpioSetInterruptType(&instance[index], FGPIO_IRQ_TYPE_EDGE_FALLING);
130 break;
131 case PIN_IRQ_MODE_LOW_LEVEL:
132 FGpioSetInterruptType(&instance[index], FGPIO_IRQ_TYPE_LEVEL_LOW);
133 break;
134 case PIN_IRQ_MODE_HIGH_LEVEL:
135 FGpioSetInterruptType(&instance[index], FGPIO_IRQ_TYPE_LEVEL_HIGH);
136 break;
137 default:
138 LOG_E("Do not spport irq_mode: %d\n", mode);
139 break;
140 }
141
142 FGpioRegisterInterruptCB(&instance[index], (FGpioInterruptCallback)hdr, &instance[index]); /* register intr callback */
143 rt_hw_interrupt_enable(level);
144
145 return RT_EOK;
146 }
147
drv_pin_detach_irq(struct rt_device * device,rt_base_t pin)148 rt_err_t drv_pin_detach_irq(struct rt_device *device, rt_base_t pin)
149 {
150 FGpio *instance = (FGpio *)device->user_data;
151 u32 index = (u32)pin;
152 FGpioIntrMap *map = &fgpio_intr_map[instance[index].config.ctrl];
153 rt_base_t level;
154
155 level = rt_hw_interrupt_disable();
156
157 if (instance[index].config.cap == FGPIO_CAP_IRQ_BY_PIN)
158 {
159 map->irq_cbs[instance[index].config.pin] = NULL;
160 }
161 rt_hw_interrupt_enable(level);
162
163 return RT_EOK;
164 }
165
drv_pin_irq_enable(struct rt_device * device,rt_base_t pin,rt_uint8_t enabled)166 rt_err_t drv_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
167 {
168 FGpio *instance = (FGpio *)device->user_data;
169 u32 index = (u32)pin;
170
171 FGpioSetInterruptMask(&instance[index], enabled);
172
173 return RT_EOK;
174 }
175
176 const struct rt_pin_ops drv_pin_ops =
177 {
178 .pin_mode = drv_pin_mode,
179 .pin_write = drv_pin_write,
180 .pin_read = drv_pin_read,
181
182 .pin_attach_irq = drv_pin_attach_irq,
183 .pin_detach_irq = drv_pin_detach_irq,
184 .pin_irq_enable = drv_pin_irq_enable,
185 .pin_get = RT_NULL
186 };
187
ft_pin_init(void)188 int ft_pin_init(void)
189 {
190 rt_err_t ret = RT_EOK;
191 ret = rt_device_pin_register("pin", &drv_pin_ops, gpio_device);
192 rt_kprintf("Register pin with return: %d\n", ret);
193 return ret;
194 }
195 INIT_DEVICE_EXPORT(ft_pin_init);