1 /*
2  * Copyright (c) 2006-2023, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Email: opensource_embedded@phytium.com.cn
7  *
8  * Change Logs:
9  * Date        Author       Notes
10  * 2022-07-07  liuzhihong   first commit
11  * 2023-07-14  liuzhihong   support RT-Smart
12  */
13 #ifndef __DRV_XMAC_H__
14 #define __DRV_XMAC_H__
15 #include <rtthread.h>
16 #include <rtdevice.h>
17 
18 #ifdef BSP_USING_ETH
19 
20 #include <netif/ethernetif.h>
21 
22 #include "fxmac.h"
23 #include "fkernel.h"
24 #include "ferror_code.h"
25 #include "fassert.h"
26 #include "fxmac_bdring.h"
27 #include "eth_ieee_reg.h"
28 #include "fcpu_info.h"
29 #include "fxmac_phy.h"
30 
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34 
35 #define FREERTOS_XMAC_INIT_ERROR FT_CODE_ERR(ErrModPort, 0, 0x1)
36 #define FREERTOS_XMAC_PARAM_ERROR FT_CODE_ERR(ErrModPort, 0, 0x2)
37 #define FREERTOS_XMAC_NO_VALID_SPACE FT_CODE_ERR(ErrModPort, 0, 0x3)
38 
39 #define FXMAX_RX_BDSPACE_LENGTH    0x20000 /* default set 128KB*/
40 #define FXMAX_TX_BDSPACE_LENGTH    0x20000 /* default set 128KB*/
41 
42 #define FXMAX_RX_PBUFS_LENGTH       16
43 #define FXMAX_TX_PBUFS_LENGTH       16
44 
45 #define FXMAX_MAX_HARDWARE_ADDRESS_LENGTH 6
46 
47 #define XMAC_PHY_RESET_ENABLE 1
48 #define XMAC_PHY_RESET_DISABLE 0
49 
50 /* configuration */
51 #define FXMAC_OS_CONFIG_JUMBO  BIT(0)
52 #define FXMAC_OS_CONFIG_MULTICAST_ADDRESS_FILITER  BIT(1) /* Allow multicast address filtering  */
53 #define FXMAC_OS_CONFIG_COPY_ALL_FRAMES BIT(2) /* enable copy all frames */
54 #define FXMAC_OS_CONFIG_CLOSE_FCS_CHECK BIT(3) /* close fcs check */
55 #define FXMAC_OS_CONFIG_RX_POLL_RECV BIT(4)  /* select poll mode */
56 /* Phy */
57 #define FXMAC_PHY_SPEED_10M    10
58 #define FXMAC_PHY_SPEED_100M    100
59 #define FXMAC_PHY_SPEED_1000M    1000
60 
61 #define FXMAC_PHY_HALF_DUPLEX   0
62 #define FXMAC_PHY_FULL_DUPLEX   1
63 
64 #define MAX_FRAME_SIZE_JUMBO (FXMAC_MTU_JUMBO + FXMAC_HDR_SIZE + FXMAC_TRL_SIZE)
65 
66 /* Byte alignment of BDs */
67 #define BD_ALIGNMENT (FXMAC_DMABD_MINIMUM_ALIGNMENT*2)
68 
69 /*  frame queue */
70 #define PQ_QUEUE_SIZE 4096
71 
72 #define LINK_THREAD_STACK_LENGTH 0x20400
73 
74 
75 typedef struct
76 {
77     uintptr data[PQ_QUEUE_SIZE];
78     int head, tail, len;
79 } PqQueue;
80 
81 typedef enum
82 {
83     FXMAC_OS_INTERFACE_SGMII = 0,
84     FXMAC_OS_INTERFACE_RMII,
85     FXMAC_OS_INTERFACE_RGMII,
86     FXMAC_OS_INTERFACE_LENGTH
87 } FXmacRtThreadInterface;
88 
89 
90 typedef struct
91 {
92     u8 rx_bdspace[FXMAX_RX_BDSPACE_LENGTH] __attribute__((aligned(128))); /* 接收bd 缓冲区 */
93     u8 tx_bdspace[FXMAX_RX_BDSPACE_LENGTH] __attribute__((aligned(128))); /* 发送bd 缓冲区 */
94 
95     uintptr rx_pbufs_storage[FXMAX_RX_PBUFS_LENGTH];
96     uintptr tx_pbufs_storage[FXMAX_TX_PBUFS_LENGTH];
97 
98 } FXmacNetifBuffer;
99 
100 typedef struct
101 {
102     u32 instance_id;
103     FXmacRtThreadInterface interface;
104     u32 autonegotiation; /* 1 is autonegotiation ,0 is manually set */
105     u32 phy_speed;  /* FXMAC_PHY_SPEED_XXX */
106     u32 phy_duplex; /* FXMAC_PHY_XXX_DUPLEX */
107 } FXmacOsControl;
108 
109 
110 typedef struct
111 {
112     struct eth_device parent; /* inherit from ethernet device */
113 
114     FXmac instance; /* Xmac controller */
115     FXmacOsControl mac_config;
116 
117     FXmacNetifBuffer buffer; /* DMA buffer */
118 
119     /* queue to store overflow packets */
120     PqQueue recv_q;
121     PqQueue send_q;
122 
123     /* configuration */
124     u32 config;
125     u32 is_link_up;
126     rt_uint8_t hwaddr[FXMAX_MAX_HARDWARE_ADDRESS_LENGTH]; /* MAC address */
127 
128     struct rt_thread _link_thread; /* link detect thread */
129     rt_uint8_t _link_thread_stack[LINK_THREAD_STACK_LENGTH];/* link detect thread stack*/
130 } FXmacOs;
131 
132 enum lwip_port_link_status
133 {
134     ETH_LINK_UNDEFINED = 0,
135     ETH_LINK_UP,
136     ETH_LINK_DOWN,
137     ETH_LINK_NEGOTIATING
138 };
139 
140 
141 
142 #ifdef __cplusplus
143 }
144 #endif
145 
146 #endif // !
147 
148 #endif
149