1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2018-11-22 Jesven first version
9 */
10
11 #include <rthw.h>
12 #include <rtthread.h>
13 #include <stdint.h>
14
15 #include "mmu.h"
16 #include "board.h"
17
18 #define TIMER01_HW_BASE_PHY 0x10011000
19 #define TIMER23_HW_BASE_PHY 0x10012000
20
21 void* timer01_hw_base;
22 void* timer23_hw_base;
23
24 #define TIMER01_HW_BASE timer01_hw_base
25 #define TIMER23_HW_BASE timer23_hw_base
26
27 #define TIMER_LOAD(hw_base) __REG32(hw_base + 0x00)
28 #define TIMER_VALUE(hw_base) __REG32(hw_base + 0x04)
29 #define TIMER_CTRL(hw_base) __REG32(hw_base + 0x08)
30 #define TIMER_CTRL_ONESHOT (1 << 0)
31 #define TIMER_CTRL_32BIT (1 << 1)
32 #define TIMER_CTRL_DIV1 (0 << 2)
33 #define TIMER_CTRL_DIV16 (1 << 2)
34 #define TIMER_CTRL_DIV256 (2 << 2)
35 #define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */
36 #define TIMER_CTRL_PERIODIC (1 << 6)
37 #define TIMER_CTRL_ENABLE (1 << 7)
38
39 #define TIMER_INTCLR(hw_base) __REG32(hw_base + 0x0c)
40 #define TIMER_RIS(hw_base) __REG32(hw_base + 0x10)
41 #define TIMER_MIS(hw_base) __REG32(hw_base + 0x14)
42 #define TIMER_BGLOAD(hw_base) __REG32(hw_base + 0x18)
43
44 #define TIMER_LOAD(hw_base) __REG32(hw_base + 0x00)
45 #define TIMER_VALUE(hw_base) __REG32(hw_base + 0x04)
46 #define TIMER_CTRL(hw_base) __REG32(hw_base + 0x08)
47 #define TIMER_CTRL_ONESHOT (1 << 0)
48 #define TIMER_CTRL_32BIT (1 << 1)
49 #define TIMER_CTRL_DIV1 (0 << 2)
50 #define TIMER_CTRL_DIV16 (1 << 2)
51 #define TIMER_CTRL_DIV256 (2 << 2)
52 #define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */
53 #define TIMER_CTRL_PERIODIC (1 << 6)
54 #define TIMER_CTRL_ENABLE (1 << 7)
55
56 #define TIMER_INTCLR(hw_base) __REG32(hw_base + 0x0c)
57 #define TIMER_RIS(hw_base) __REG32(hw_base + 0x10)
58 #define TIMER_MIS(hw_base) __REG32(hw_base + 0x14)
59 #define TIMER_BGLOAD(hw_base) __REG32(hw_base + 0x18)
60
61 void* sys_ctrl;
62 #define SYS_CTRL __REG32(sys_ctrl)
63 void* timer_hw_base;
64 #define TIMER_HW_BASE timer_hw_base
65
rt_hw_timer_isr(int vector,void * param)66 static void rt_hw_timer_isr(int vector, void *param)
67 {
68 rt_tick_increase();
69 /* clear interrupt */
70 TIMER_INTCLR(TIMER_HW_BASE) = 0x01;
71 }
72
rt_hw_timer_init(void)73 int rt_hw_timer_init(void)
74 {
75 rt_uint32_t val;
76
77 #ifdef RT_USING_SMART
78 sys_ctrl = (void*)rt_ioremap((void*)REALVIEW_SCTL_BASE, 0x1000);
79 timer_hw_base = (void*)rt_ioremap((void*)REALVIEW_TIMER2_3_BASE, 0x1000);
80 #else
81 sys_ctrl = (void*)REALVIEW_SCTL_BASE;
82 timer_hw_base = (void*)REALVIEW_TIMER2_3_BASE;
83 #endif
84
85 SYS_CTRL |= REALVIEW_REFCLK;
86
87 /* Setup Timer0 for generating irq */
88 val = TIMER_CTRL(TIMER_HW_BASE);
89 val &= ~TIMER_CTRL_ENABLE;
90 val |= (TIMER_CTRL_32BIT | TIMER_CTRL_PERIODIC | TIMER_CTRL_IE);
91 TIMER_CTRL(TIMER_HW_BASE) = val;
92
93 TIMER_LOAD(TIMER_HW_BASE) = 1000000/RT_TICK_PER_SECOND;
94
95 /* enable timer */
96 TIMER_CTRL(TIMER_HW_BASE) |= TIMER_CTRL_ENABLE;
97
98 rt_hw_interrupt_install(IRQ_PBA8_TIMER2_3, rt_hw_timer_isr, RT_NULL, "tick");
99 rt_hw_interrupt_umask(IRQ_PBA8_TIMER2_3);
100
101 return 0;
102 }
103 INIT_BOARD_EXPORT(rt_hw_timer_init);
104
timer_init(int timer,unsigned int preload)105 void timer_init(int timer, unsigned int preload)
106 {
107 uint32_t val;
108
109 if (timer == 0)
110 {
111 #ifdef RT_USING_SMART
112 timer01_hw_base = (void*)rt_ioremap((void*)TIMER01_HW_BASE_PHY, 0x1000);
113 #else
114 timer01_hw_base = (void*)TIMER01_HW_BASE_PHY;
115 #endif
116 /* Setup Timer0 for generating irq */
117 val = TIMER_CTRL(TIMER01_HW_BASE);
118 val &= ~TIMER_CTRL_ENABLE;
119 val |= (TIMER_CTRL_32BIT | TIMER_CTRL_PERIODIC | TIMER_CTRL_IE);
120 TIMER_CTRL(TIMER01_HW_BASE) = val;
121
122 TIMER_LOAD(TIMER01_HW_BASE) = preload;
123
124 /* enable timer */
125 TIMER_CTRL(TIMER01_HW_BASE) |= TIMER_CTRL_ENABLE;
126 }
127 else
128 {
129 #ifdef RT_USING_SMART
130 timer23_hw_base = (void*)rt_ioremap((void*)TIMER23_HW_BASE_PHY, 0x1000);
131 #else
132 timer01_hw_base = (void*)TIMER23_HW_BASE_PHY;
133 #endif
134 /* Setup Timer1 for generating irq */
135 val = TIMER_CTRL(TIMER23_HW_BASE);
136 val &= ~TIMER_CTRL_ENABLE;
137 val |= (TIMER_CTRL_32BIT | TIMER_CTRL_PERIODIC | TIMER_CTRL_IE);
138 TIMER_CTRL(TIMER23_HW_BASE) = val;
139
140 TIMER_LOAD(TIMER23_HW_BASE) = preload;
141
142 /* enable timer */
143 TIMER_CTRL(TIMER23_HW_BASE) |= TIMER_CTRL_ENABLE;
144 }
145 }
146
timer_clear_pending(int timer)147 void timer_clear_pending(int timer)
148 {
149 if (timer == 0)
150 {
151 TIMER_INTCLR(TIMER01_HW_BASE) = 0x01;
152 }
153 else
154 {
155 TIMER_INTCLR(TIMER23_HW_BASE) = 0x01;
156 }
157 }
158