1 #ifndef BCM283X_H__ 2 #define BCM283X_H__ 3 4 #include <rthw.h> 5 6 #define PER_BASE (0x3F000000) 7 #define PER_BASE_40000000 (0x40000000) 8 9 /* 10 * GPIO 11 */ 12 #define GPIO_BASE (PER_BASE + 0x200000) 13 #define GPIO_GPFSEL0 HWREG32(GPIO_BASE + 0x00) /* GPIO Function Select 0 32bit R/W */ 14 #define GPIO_GPFSEL1 HWREG32(GPIO_BASE + 0x04) /* GPIO Function Select 1 32bit R/W */ 15 #define GPIO_GPFSEL2 HWREG32(GPIO_BASE + 0x08) /* GPIO Function Select 2 32bit R/W */ 16 #define GPIO_GPFSEL4 HWREG32(GPIO_BASE + 0x10) /* GPIO Function Select 4 32bit R/W */ 17 #define GPIO_GPSET0 HWREG32(GPIO_BASE + 0x1C) 18 #define GPIO_GPCLR0 HWREG32(GPIO_BASE + 0x28) 19 #define GPIO_GPPUD HWREG32(GPIO_BASE + 0x94) /* GPIO Pin Pull-up/down Enable */ 20 #define GPIO_GPPUDCLK0 HWREG32(GPIO_BASE + 0x98) /* GPIO Pin Pull-up/down Enable Clock 0 */ 21 #define GPIO_GPPUDCLK1 HWREG32(GPIO_BASE + 0x9C) /* GPIO Pin Pull-up/down Enable Clock 1 */ 22 23 /* 24 * Interrupt Controler 25 */ 26 #define IRQ_BASE (PER_BASE + 0xB200) 27 #define IRQ_PEND_BASIC HWREG32(IRQ_BASE + 0x00) 28 #define IRQ_PEND1 HWREG32(IRQ_BASE + 0x04) 29 #define IRQ_PEND2 HWREG32(IRQ_BASE + 0x08) 30 #define IRQ_FIQ_CONTROL HWREG32(IRQ_BASE + 0x0C) 31 #define IRQ_ENABLE1 HWREG32(IRQ_BASE + 0x10) 32 #define IRQ_ENABLE2 HWREG32(IRQ_BASE + 0x14) 33 #define IRQ_ENABLE_BASIC HWREG32(IRQ_BASE + 0x18) 34 #define IRQ_DISABLE1 HWREG32(IRQ_BASE + 0x1C) 35 #define IRQ_DISABLE2 HWREG32(IRQ_BASE + 0x20) 36 #define IRQ_DISABLE_BASIC HWREG32(IRQ_BASE + 0x24) 37 38 /* 39 * System Timer 40 */ 41 #define STIMER_BASE (PER_BASE + 0x3000) 42 #define STIMER_CS HWREG32(STIMER_BASE + 0x00) 43 #define STIMER_CLO HWREG32(STIMER_BASE + 0x04) 44 #define STIMER_CHI HWREG32(STIMER_BASE + 0x08) 45 #define STIMER_C0 HWREG32(STIMER_BASE + 0x0C) 46 #define STIMER_C1 HWREG32(STIMER_BASE + 0x10) 47 #define STIMER_C2 HWREG32(STIMER_BASE + 0x14) 48 #define STIMER_C3 HWREG32(STIMER_BASE + 0x18) 49 50 /* 51 * ARM Timer 52 */ 53 #define ARM_TIMER_BASE (PER_BASE + 0xB000) 54 55 #define ARM_TIMER_LOAD HWREG32(ARM_TIMER_BASE + 0x400) 56 #define ARM_TIMER_VALUE HWREG32(ARM_TIMER_BASE + 0x404) 57 #define ARM_TIMER_CTRL HWREG32(ARM_TIMER_BASE + 0x408) 58 #define ARM_TIMER_IRQCLR HWREG32(ARM_TIMER_BASE + 0x40C) 59 #define ARM_TIMER_RAWIRQ HWREG32(ARM_TIMER_BASE + 0x410) 60 #define ARM_TIMER_MASKIRQ HWREG32(ARM_TIMER_BASE + 0x414) 61 #define ARM_TIMER_RELOAD HWREG32(ARM_TIMER_BASE + 0x418) 62 #define ARM_TIMER_PREDIV HWREG32(ARM_TIMER_BASE + 0x41C) 63 #define ARM_TIMER_CNTR HWREG32(ARM_TIMER_BASE + 0x420) 64 65 /* 66 * Core Timer 67 */ 68 #define CTIMER_CTL HWREG32(PER_BASE_40000000 + 0x00) /* Control register */ 69 #define CTIMER_PRE HWREG32(PER_BASE_40000000 + 0x08) /* Core timer prescaler */ 70 #define CTIMER_LS32B HWREG32(PER_BASE_40000000 + 0x1C) /* Core timer access LS 32 bits */ 71 #define CTIMER_MS32B HWREG32(PER_BASE_40000000 + 0x20) /* Core timer access MS 32 bits */ 72 73 /* 74 * ARM Core Timer 75 */ 76 #define C0TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x40) /* Core0 timers Interrupt control */ 77 #define C1TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x44) /* Core1 timers Interrupt control */ 78 #define C2TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x48) /* Core2 timers Interrupt control */ 79 #define C3TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x4C) /* Core3 timers Interrupt control */ 80 81 /* 82 * ARM Core Mailbox interrupt 83 */ 84 #define C0MB_INTCTL HWREG32(PER_BASE_40000000 + 0x50) /* Core0 Mailboxes Interrupt control */ 85 #define C1MB_INTCTL HWREG32(PER_BASE_40000000 + 0x54) /* Core1 Mailboxes Interrupt control */ 86 #define C2MB_INTCTL HWREG32(PER_BASE_40000000 + 0x58) /* Core2 Mailboxes Interrupt control */ 87 #define C3MB_INTCTL HWREG32(PER_BASE_40000000 + 0x5C) /* Core3 Mailboxes Interrupt control */ 88 89 /* 90 * ARM Core IRQ/FIQ status 91 */ 92 #define C0_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x60) /* Core0 IRQ Source */ 93 #define C1_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x64) /* Core1 IRQ Source */ 94 #define C2_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x68) /* Core2 IRQ Source */ 95 #define C3_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x6C) /* Core3 IRQ Source */ 96 #define C0_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x70) /* Core0 FIQ Source */ 97 #define C1_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x74) /* Core1 FIQ Source */ 98 #define C2_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x78) /* Core2 FIQ Source */ 99 #define C3_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x7C) /* Core3 FIQ Source */ 100 101 #define IRQ_ARM_TIMER 0 102 #define IRQ_ARM_MAILBOX 1 103 #define IRQ_ARM_DB0 2 104 #define IRQ_ARM_DB1 3 105 #define IRQ_ARM_GPU0_HALT 4 106 #define IRQ_ARM_GPU1_HALT 5 107 #define IRQ_ARM_ILLEGAL_ACC1 6 108 #define IRQ_ARM_ILLEGAL_ACC0 7 109 110 #define IRQ_AUX 29 111 #define IRQ_IIC_SPI_SLV 43 112 #define IRQ_PWA0 45 113 #define IRQ_PWA1 46 114 #define IRQ_SMI 48 115 #define IRQ_GPIO0 49 116 #define IRQ_GPIO1 50 117 #define IRQ_GPIO2 51 118 #define IRQ_GPIO3 52 119 #define IRQ_IIC 53 120 #define IRQ_SPI 54 121 #define IRQ_PCM 55 122 #define IRQ_UART 57 123 124 #endif 125 126