1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2011-09-15 Bernard first version
9 */
10 #include "raspi.h"
11 #ifndef __CP15_H__
12 #define __CP15_H__
13
14 #ifndef __STATIC_FORCEINLINE
15 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
16 #endif
17
18 #define __WFI() __asm__ volatile ("wfi":::"memory")
19
20 #define __WFE() __asm__ volatile ("wfe":::"memory")
21
22 #define __SEV() __asm__ volatile ("sev")
23
__ISB(void)24 __STATIC_FORCEINLINE void __ISB(void)
25 {
26 __asm__ volatile ("isb 0xF":::"memory");
27 }
28
29
30 /**
31 \brief Data Synchronization Barrier
32 \details Acts as a special kind of Data Memory Barrier.
33 It completes when all explicit memory accesses before this instruction complete.
34 */
__DSB(void)35 __STATIC_FORCEINLINE void __DSB(void)
36 {
37 __asm__ volatile ("dsb 0xF":::"memory");
38 }
39
40 /**
41 \brief Data Memory Barrier
42 \details Ensures the apparent order of the explicit memory operations before
43 and after the instruction, without ensuring their completion.
44 */
45
__DMB(void)46 __STATIC_FORCEINLINE void __DMB(void)
47 {
48 __asm__ volatile ("dmb 0xF":::"memory");
49 }
50
51
52 #ifdef RT_USING_SMP
send_ipi_msg(int cpu,int ipi_vector)53 static inline void send_ipi_msg(int cpu, int ipi_vector)
54 {
55 IPI_MAILBOX_SET(cpu) = 1 << ipi_vector;
56 }
57
setup_bootstrap_addr(int cpu,int addr)58 static inline void setup_bootstrap_addr(int cpu, int addr)
59 {
60 CORE_MAILBOX3_SET(cpu) = addr;
61 }
62
enable_cpu_ipi_intr(int cpu)63 static inline void enable_cpu_ipi_intr(int cpu)
64 {
65 COREMB_INTCTL(cpu) = IPI_MAILBOX_INT_MASK;
66 }
67
enable_cpu_timer_intr(int cpu)68 static inline void enable_cpu_timer_intr(int cpu)
69 {
70 CORETIMER_INTCTL(cpu) = 0x8;
71 }
72
enable_cntv(void)73 static inline void enable_cntv(void)
74 {
75 rt_uint32_t cntv_ctl;
76 cntv_ctl = 1;
77 asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
78 }
79
disable_cntv(void)80 static inline void disable_cntv(void)
81 {
82 rt_uint32_t cntv_ctl;
83 cntv_ctl = 0;
84 asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
85 }
86
mask_cntv(void)87 static inline void mask_cntv(void)
88 {
89 rt_uint32_t cntv_ctl;
90 cntv_ctl = 2;
91 asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
92 }
93
unmask_cntv(void)94 static inline void unmask_cntv(void)
95 {
96 rt_uint32_t cntv_ctl;
97 cntv_ctl = 1;
98 asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
99 }
100
read_cntvct(void)101 static inline rt_uint64_t read_cntvct(void)
102 {
103 rt_uint32_t val,val1;
104 asm volatile ("mrrc p15, 1, %0, %1, c14" : "=r" (val),"=r" (val1));
105 return (val);
106 }
107
read_cntvoff(void)108 static inline rt_uint64_t read_cntvoff(void)
109 {
110
111 rt_uint64_t val;
112 asm volatile ("mrrc p15, 4, %Q0, %R0, c14" : "=r" (val));
113 return (val);
114 }
115
read_cntv_tval(void)116 static inline rt_uint32_t read_cntv_tval(void)
117 {
118 rt_uint32_t val;
119 asm volatile ("mrc p15, 0, %0, c14, c3, 0" : "=r"(val));
120 return val;
121 }
122
123
write_cntv_tval(rt_uint32_t val)124 static inline void write_cntv_tval(rt_uint32_t val)
125 {
126 asm volatile ("mcr p15, 0, %0, c14, c3, 0" :: "r"(val));
127 return;
128 }
129
read_cntfrq(void)130 static inline rt_uint32_t read_cntfrq(void)
131 {
132 rt_uint32_t val;
133 asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val));
134 return val;
135 }
136
137
read_cntctrl(void)138 static inline rt_uint32_t read_cntctrl(void)
139 {
140 rt_uint32_t val;
141 asm volatile ("mrc p15, 0, %0, c14, c1, 0" : "=r"(val));
142 return val;
143 }
144
write_cntctrl(rt_uint32_t val)145 static inline rt_uint32_t write_cntctrl(rt_uint32_t val)
146 {
147
148 asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val));
149 return val;
150 }
151 #endif
152
153 unsigned long rt_cpu_get_smp_id(void);
154
155 void rt_cpu_mmu_disable(void);
156 void rt_cpu_mmu_enable(void);
157 void rt_cpu_tlb_set(volatile unsigned long*);
158
159 void rt_cpu_dcache_clean_flush(void);
160 void rt_cpu_icache_flush(void);
161
162 void rt_cpu_vector_set_base(unsigned int addr);
163 void rt_hw_mmu_init(void);
164 void rt_hw_vector_init(void);
165
166 void set_timer_counter(unsigned int counter);
167 void set_timer_control(unsigned int control);
168 #endif
169