1 #ifndef MMU_H__ 2 #define MMU_H__ 3 #include <rtthread.h> 4 #include <rthw.h> 5 #include <board.h> 6 #include "cp15.h" 7 8 #define DESC_SEC (0x2) 9 #define CB (3 << 2) //cache_on, write_back 10 #define CNB (2 << 2) //cache_on, write_through 11 #define NCB (1 << 2) //cache_off,WR_BUF on 12 #define NCNB (0 << 2) //cache_off,WR_BUF off 13 #define AP_RW (3 << 10) //supervisor=RW, user=RW 14 #define AP_RO (2 << 10) //supervisor=RW, user=RO 15 #define XN (1 << 4) // eXecute Never 16 #define SHARED (1 << 16) /* shareable */ 17 #define SHAREDEVICE (1 << 2) /* shared device */ 18 #define STRONGORDER (0 << 2) /* strong ordered */ 19 #define MEMWBWA ((1 << 12) | (3 << 2)) /* write back, write allocate */ 20 21 #define DOMAIN_FAULT (0x0) 22 #define DOMAIN_CHK (0x1) 23 #define DOMAIN_NOTCHK (0x3) 24 #define DOMAIN0 (0x0 << 5) 25 #define DOMAIN1 (0x1 << 5) 26 27 #define DOMAIN0_ATTR (DOMAIN_CHK << 0) 28 #define DOMAIN1_ATTR (DOMAIN_FAULT << 2) 29 30 /* Read/Write, cache, write back */ 31 #define RW_CB (AP_RW | DOMAIN0 | CB | DESC_SEC) 32 /* Read/Write, cache, write through */ 33 #define RW_CNB (AP_RW | DOMAIN0 | CNB | DESC_SEC) 34 /* Read/Write without cache and write buffer */ 35 #define RW_NCNB (AP_RW | DOMAIN0 | NCNB | DESC_SEC) 36 /* Read/Write without cache and write buffer, no execute */ 37 #define RW_NCNBXN (AP_RW | DOMAIN0 | NCNB | DESC_SEC | XN) 38 /* Read/Write without cache and write buffer */ 39 #define RW_FAULT (AP_RW | DOMAIN1 | NCNB | DESC_SEC) 40 41 /* device mapping type */ 42 #define DEVICE_MEM (SHARED | SHAREDEVICE | RW_NCNBXN) 43 /* normal memory mapping type */ 44 #define NORMAL_MEM (SHARED | AP_RW | DOMAIN0 | MEMWBWA | DESC_SEC) 45 #define STRONG_ORDER_MEM (SHARED | AP_RO | XN | DESC_SEC) 46 #define BUS_ADDRESS(phys) (((phys) & ~0xC0000000) | 0xC0000000) 47 48 void rt_hw_change_mmu_table(rt_uint32_t vaddrStart, 49 rt_uint32_t size, 50 rt_uint32_t paddrStart, rt_uint32_t attr); 51 #endif 52