1 /*
2  * Copyright (c) 2006-2021, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author         Notes
8  * 2019-07-29     zdzn           first version
9  */
10 
11 #include "drv_i2c.h"
12 
i2c_read_or_write(volatile rt_uint32_t base,rt_uint8_t * buf,rt_uint32_t len,rt_uint8_t flag)13 rt_uint8_t i2c_read_or_write(volatile rt_uint32_t base, rt_uint8_t* buf, rt_uint32_t len, rt_uint8_t flag)
14 {
15     rt_uint32_t status;
16     rt_uint32_t remaining = len;
17     rt_uint32_t i = 0;
18     rt_uint8_t reason = BCM283X_I2C_REASON_OK;
19 
20     /* Clear FIFO */
21     BCM283X_BSC_C(base) |= (BSC_C_CLEAR_1 & BSC_C_CLEAR_1);
22     /* Clear Status */
23     BCM283X_BSC_S(base) = BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE;
24     /* Set Data Length */
25     BCM283X_BSC_DLEN(base) = len;
26     if (flag)
27     {
28         /* Start read */
29         BCM283X_BSC_C(base) = BSC_C_I2CEN | BSC_C_ST | BSC_C_READ;
30         /* wait for transfer to complete */
31         while (!(BCM283X_BSC_S(base) & BSC_S_DONE))
32         {
33             /* we must empty the FIFO as it is populated and not use any delay */
34             while (remaining && (BCM283X_BSC_S(base) & BSC_S_RXD))
35             {
36                 /* Read from FIFO, no barrier */
37                 buf[i] = BCM283X_BSC_FIFO(base);
38                 i++;
39                 remaining--;
40             }
41         }
42         /* transfer has finished - grab any remaining stuff in FIFO */
43         while (remaining && (BCM283X_BSC_S(base) & BSC_S_RXD))
44         {
45             /* Read from FIFO, no barrier */
46             buf[i] = BCM283X_BSC_FIFO(base);
47             i++;
48             remaining--;
49         }
50     }
51     else
52     {
53         /* pre populate FIFO with max buffer */
54         while (remaining && (i < BSC_FIFO_SIZE))
55         {
56             BCM283X_BSC_FIFO(base) = buf[i];
57             i++;
58             remaining--;
59         }
60 
61         /* Enable device and start transfer */
62         BCM283X_BSC_C(base) = BSC_C_I2CEN | BSC_C_ST;
63 
64         /* Transfer is over when BCM2835_BSC_S_DONE */
65         while (!(BCM283X_BSC_S(base) & BSC_S_DONE))
66         {
67             while (remaining && (BCM283X_BSC_S(base) & BSC_S_TXD))
68             {
69                 /* Write to FIFO */
70                 BCM283X_BSC_FIFO(base) = buf[i];
71                 i++;
72                 remaining--;
73             }
74         }
75     }
76 
77     status = BCM283X_BSC_S(base);
78     if (status & BSC_S_ERR)
79     {
80         reason = BCM283X_I2C_REASON_ERROR_NACK;
81     }
82     else if (status & BSC_S_CLKT)
83     {
84         reason = BCM283X_I2C_REASON_ERROR_CLKT;
85     }
86     else if (remaining)
87     {
88         reason = BCM283X_I2C_REASON_ERROR_DATA;
89     }
90     BCM283X_BSC_C(base) |= (BSC_S_DONE & BSC_S_DONE);
91 
92     return reason;
93 }
94 
95 struct raspi_i2c_hw_config
96 {
97     rt_uint8_t bsc_num;
98     rt_uint8_t sdl_pin;
99     rt_uint8_t scl_pin;
100     rt_uint8_t sdl_mode;
101     rt_uint8_t scl_mode;
102 };
103 
104 #if (defined(BSP_USING_I2C0) || defined(BSP_USING_I2C1))
105 
106 static rt_ssize_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
107                                     struct rt_i2c_msg msgs[],
108                                     rt_uint32_t num);
109 static rt_ssize_t raspi_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
110                                     struct rt_i2c_msg msgs[],
111                                     rt_uint32_t num);
112 static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus,
113                                       int cmd,
114                                       void *args);
115 
116 static rt_uint32_t i2c_byte_wait_us = 0;
raspi_i2c_mst_xfer(struct rt_i2c_bus_device * bus,struct rt_i2c_msg msgs[],rt_uint32_t num)117 static rt_ssize_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
118                                     struct rt_i2c_msg msgs[],
119                                     rt_uint32_t num)
120 {
121     rt_size_t i;
122     rt_uint8_t reason;
123     RT_ASSERT(bus != RT_NULL);
124 
125     volatile rt_uint32_t base = (volatile rt_uint32_t)(bus->parent.user_data);
126 
127     if (bus->parent.user_data == 0)
128         base = BCM283X_BSC0_BASE;
129     else
130         base = BCM283X_BSC1_BASE;
131 
132     BCM283X_BSC_A(base) = msgs->addr;
133 
134     for (i = 0; i < num; i++)
135     {
136         if (msgs[i].flags & RT_I2C_RD)
137             reason = i2c_read_or_write(base, msgs->buf, msgs->len, 1);
138         else
139             reason = i2c_read_or_write(base, msgs->buf, msgs->len, 0);
140     }
141     return (reason == 0)? i : 0;
142 }
143 
raspi_i2c_slv_xfer(struct rt_i2c_bus_device * bus,struct rt_i2c_msg msgs[],rt_uint32_t num)144 static rt_ssize_t raspi_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
145                                     struct rt_i2c_msg msgs[],
146                                     rt_uint32_t num)
147 {
148     return 0;
149 }
raspi_i2c_bus_control(struct rt_i2c_bus_device * bus,int cmd,void * args)150 static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus,
151                                       int cmd,
152                                       void *args)
153 {
154     return RT_EOK;
155 }
156 
157 static const struct rt_i2c_bus_device_ops raspi_i2c_ops =
158 {
159     .master_xfer = raspi_i2c_mst_xfer,
160     .slave_xfer = raspi_i2c_slv_xfer,
161     .i2c_bus_control = raspi_i2c_bus_control,
162 };
163 
164 
raspi_i2c_configure(struct raspi_i2c_hw_config * cfg)165 static rt_err_t raspi_i2c_configure(struct raspi_i2c_hw_config *cfg)
166 {
167     RT_ASSERT(cfg != RT_NULL);
168 
169     volatile rt_uint32_t base = cfg->scl_mode ? BCM283X_BSC1_BASE : BCM283X_BSC0_BASE;
170 
171     GPIO_FSEL(cfg->sdl_pin, cfg->sdl_mode); /* SDA */
172     GPIO_FSEL(cfg->scl_pin, cfg->scl_mode); /* SCL */
173 
174     /* use 0xFFFE mask to limit a max value and round down any odd number */
175     rt_uint32_t divider = (BCM283X_CORE_CLK_HZ / 10000) & 0xFFFE;
176     BCM283X_BSC_DIV(base) = (rt_uint16_t) divider;
177     i2c_byte_wait_us = (divider * 1000000 * 9 / BCM283X_CORE_CLK_HZ);
178 
179     return RT_EOK;
180 }
181 #endif
182 
183 #if defined (BSP_USING_I2C0)
184 #define I2C0_BUS_NAME    "i2c0"
185 static struct raspi_i2c_hw_config hw_device0 =
186 {
187     .bsc_num = 0,
188     .sdl_pin = RPI_GPIO_P1_27,
189     .scl_pin = RPI_GPIO_P1_28,
190     .sdl_mode = BCM283X_GPIO_FSEL_ALT0,
191     .scl_mode = BCM283X_GPIO_FSEL_ALT0,
192 };
193 
194 struct rt_i2c_bus_device device0 =
195 {
196     .ops = &raspi_i2c_ops,
197 };
198 
199 #endif
200 
201 #if defined (BSP_USING_I2C1)
202 #define I2C1_BUS_NAME    "i2c1"
203 static struct raspi_i2c_hw_config hw_device1 =
204 {
205     .bsc_num = 1,
206     .sdl_pin = RPI_GPIO_P1_03,
207     .scl_pin = RPI_GPIO_P1_05,
208     .sdl_mode = BCM283X_GPIO_FSEL_ALT0,
209     .scl_mode = BCM283X_GPIO_FSEL_ALT0,
210 };
211 struct rt_i2c_bus_device device1 =
212 {
213     .ops = &raspi_i2c_ops,
214 };
215 
216 #endif
217 
rt_hw_i2c_init(void)218 int rt_hw_i2c_init(void)
219 {
220 #if defined(BSP_USING_I2C0)
221     device0.parent.user_data = (void *)0;
222     raspi_i2c_configure(&hw_device0);
223     rt_i2c_bus_device_register(&device0, I2C0_BUS_NAME);
224 #endif
225 
226 #if defined(BSP_USING_I2C1)
227     device1.parent.user_data = (void *)1;
228     raspi_i2c_configure(&hw_device1);
229     rt_i2c_bus_device_register(&device1, I2C1_BUS_NAME);
230 #endif
231 
232     return 0;
233 }
234 INIT_DEVICE_EXPORT(rt_hw_i2c_init);
235