1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2019-07-29 zdzn first version
9 * 2021-12-28 GuEe-GUI add smp support
10 */
11
12 #include <rthw.h>
13 #include <rtthread.h>
14
15 #include "board.h"
16 #include "drv_uart.h"
17 #include "drv_timer.h"
18
19 #include "gtimer.h"
20 #include "cpuport.h"
21 #include "interrupt.h"
22 #include "mmu.h"
23 #include "raspi.h"
24
25 struct mem_desc platform_mem_desc[] =
26 {
27 {0, 0x6400000, 0, NORMAL_MEM},
28 {0xc00000, 0xc01000, 0xc00000, DEVICE_MEM}, /* mbox */
29 {0x3f000000, 0x3f200000, 0x3f000000, DEVICE_MEM}, /* timer */
30 {0x3f200000, 0x3f216000, 0x3f200000, DEVICE_MEM}, /* uart */
31 {0x40000000, 0x40200000, 0x40000000, DEVICE_MEM}, /* core timer */
32 {0x3F300000, 0x3F301000, 0x3F300000, DEVICE_MEM}, /* sdio */
33 {0x3f804000, 0x3f805000, 0x3f804000, DEVICE_MEM}, /* i2c0 */
34 {0x3f205000, 0x3f206000, 0x3f205000, DEVICE_MEM}, /* i2c1 */
35 };
36
37 const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]);
38
39 #if defined(BSP_USING_CORETIMER) || defined(RT_USING_SMP)
40 static volatile rt_uint64_t timer_step;
41 #define BSP_USING_CORETIMER
42 #endif
43
rt_hw_timer_isr(int vector,void * parameter)44 void rt_hw_timer_isr(int vector, void *parameter)
45 {
46 #ifdef BSP_USING_CORETIMER
47 rt_hw_set_gtimer_val(timer_step);
48 #else
49 ARM_TIMER_IRQCLR = 0;
50 #endif
51 rt_tick_increase();
52 }
53
54 rt_uint8_t core_timer_flag;
55
rt_hw_timer_init(void)56 void rt_hw_timer_init(void)
57 {
58 rt_hw_interrupt_install(IRQ_ARM_TIMER, rt_hw_timer_isr, RT_NULL, "tick");
59 rt_hw_interrupt_umask(IRQ_ARM_TIMER);
60 #ifdef BSP_USING_CORETIMER
61 rt_hw_isb();
62 timer_step = rt_hw_get_gtimer_frq();
63 rt_hw_dsb();
64 timer_step /= RT_TICK_PER_SECOND;
65
66 rt_hw_gtimer_enable();
67 rt_hw_set_gtimer_val(timer_step);
68 #ifdef RT_USING_SMP
69 core_timer_enable(rt_hw_cpu_id());
70 #else
71 core_timer_enable(0);
72 #endif
73 #else
74 __DSB();
75 /* timer_clock = apb_clock/(pre_divider + 1) */
76 ARM_TIMER_PREDIV = (250 - 1);
77
78 ARM_TIMER_RELOAD = 0;
79 ARM_TIMER_LOAD = 0;
80 ARM_TIMER_IRQCLR = 0;
81 ARM_TIMER_CTRL = 0;
82
83 ARM_TIMER_RELOAD = 10000;
84 ARM_TIMER_LOAD = 10000;
85
86 /* 23-bit counter, enable interrupt, enable timer */
87 ARM_TIMER_CTRL = (1 << 1) | (1 << 5) | (1 << 7);
88 #endif
89 }
90
idle_wfi(void)91 void idle_wfi(void)
92 {
93 asm volatile ("wfi");
94 }
95
96 /**
97 * Initialize the Hardware related stuffs. Called from rtthread_startup()
98 * after interrupt disabled.
99 */
rt_hw_board_init(void)100 void rt_hw_board_init(void)
101 {
102 extern void *MMUTable;
103 rt_hw_mmu_map_init(&rt_kernel_space, (void*)0x80000000, 0x10000000, MMUTable, 0);
104 rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, platform_mem_desc_size);
105
106 /* initialize hardware interrupt */
107 rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device
108
109 /* initialize uart */
110 rt_hw_uart_init(); // driver/drv_uart.c
111 /* initialize timer for os tick */
112 rt_hw_timer_init();
113 rt_thread_idle_sethook(idle_wfi);
114
115 #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
116 /* set console device */
117 rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
118 #endif
119
120 #ifdef RT_USING_HEAP
121 /* initialize memory system */
122 rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
123 rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
124 #endif
125
126 #ifdef RT_USING_COMPONENTS_INIT
127 rt_components_board_init();
128 #endif
129
130 #ifdef RT_USING_SMP
131 /* install IPI handle */
132 rt_hw_ipi_handler_install(IRQ_ARM_MAILBOX, rt_scheduler_ipi_handler);
133 rt_hw_interrupt_umask(IRQ_ARM_MAILBOX);
134 enable_cpu_ipi_intr(0);
135 #endif
136 }
137
138 #ifdef RT_USING_SMP
139 static unsigned long cpu_release_paddr[] =
140 {
141 [0] = 0xd8,
142 [1] = 0xe0,
143 [2] = 0xe8,
144 [3] = 0xf0,
145 [4] = 0
146 };
147
rt_hw_secondary_cpu_up(void)148 void rt_hw_secondary_cpu_up(void)
149 {
150 int i;
151 extern void secondary_cpu_start(void);
152
153 for (i = 1; i < RT_CPUS_NR && cpu_release_paddr[i]; ++i)
154 {
155 __asm__ volatile ("str %0, [%1]"::"rZ"((unsigned long)secondary_cpu_start), "r"(cpu_release_paddr[i]));
156 rt_hw_dcache_flush_range(cpu_release_paddr[i], sizeof(cpu_release_paddr[i]));
157 __DSB();
158 __SEV();
159 }
160 }
161
secondary_cpu_c_start(void)162 void secondary_cpu_c_start(void)
163 {
164 int id = rt_hw_cpu_id();
165
166 rt_hw_mmu_init();
167 rt_hw_spin_lock(&_cpus_lock);
168
169 rt_hw_vector_init();
170 rt_hw_timer_init();
171 enable_cpu_ipi_intr(id);
172
173 rt_kprintf("\rcall cpu %d on success\n", id);
174
175 rt_system_scheduler_start();
176 }
177
rt_hw_secondary_cpu_idle_exec(void)178 void rt_hw_secondary_cpu_idle_exec(void)
179 {
180 __WFE();
181 }
182
183 #endif
184