1 /*
2  * Copyright (c) 2006-2021, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author         Notes
8  * 2019-07-29     zdzn           first version
9  */
10 
11 #include "raspi.h"
12 #include "drv_i2c.h"
13 
14 //Maybe redefined
15 typedef unsigned long                   rt_ubase_t;
16 typedef rt_ubase_t                      rt_size_t;
17 
i2c_read_or_write(volatile rt_uint32_t base,rt_uint8_t * buf,rt_uint32_t len,rt_uint8_t flag)18 rt_uint8_t i2c_read_or_write(volatile rt_uint32_t base, rt_uint8_t* buf, rt_uint32_t len, rt_uint8_t flag)
19 {
20     rt_uint32_t status;
21     rt_uint32_t remaining = len;
22     rt_uint32_t i = 0;
23     rt_uint8_t reason = BCM283X_I2C_REASON_OK;
24 
25     /* Clear FIFO */
26     BCM283X_BSC_C(base) |= (BSC_C_CLEAR_1 & BSC_C_CLEAR_1);
27     /* Clear Status */
28     BCM283X_BSC_S(base) = BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE;
29     /* Set Data Length */
30     BCM283X_BSC_DLEN(base) = len;
31     if (flag)
32     {
33         /* Start read */
34         BCM283X_BSC_C(base) = BSC_C_I2CEN | BSC_C_ST | BSC_C_READ;
35         /* wait for transfer to complete */
36         while (!(BCM283X_BSC_S(base) & BSC_S_DONE))
37         {
38             /* we must empty the FIFO as it is populated and not use any delay */
39             while (remaining && (BCM283X_BSC_S(base) & BSC_S_RXD))
40             {
41                 /* Read from FIFO, no barrier */
42                 buf[i] = BCM283X_BSC_FIFO(base);
43                 i++;
44                 remaining--;
45             }
46         }
47         /* transfer has finished - grab any remaining stuff in FIFO */
48         while (remaining && (BCM283X_BSC_S(base) & BSC_S_RXD))
49         {
50             /* Read from FIFO, no barrier */
51             buf[i] = BCM283X_BSC_FIFO(base);
52             i++;
53             remaining--;
54         }
55     }
56     else
57     {
58         /* pre populate FIFO with max buffer */
59         while (remaining && (i < BSC_FIFO_SIZE))
60         {
61             BCM283X_BSC_FIFO(base) = buf[i];
62             i++;
63             remaining--;
64         }
65 
66         /* Enable device and start transfer */
67         BCM283X_BSC_C(base) = BSC_C_I2CEN | BSC_C_ST;
68 
69         /* Transfer is over when BCM2835_BSC_S_DONE */
70         while (!(BCM283X_BSC_S(base) & BSC_S_DONE))
71         {
72             while (remaining && (BCM283X_BSC_S(base) & BSC_S_TXD))
73             {
74                 /* Write to FIFO */
75                 BCM283X_BSC_FIFO(base) = buf[i];
76                 i++;
77                 remaining--;
78             }
79         }
80     }
81 
82     status = BCM283X_BSC_S(base);
83     if (status & BSC_S_ERR)
84     {
85         reason = BCM283X_I2C_REASON_ERROR_NACK;
86     }
87     else if (status & BSC_S_CLKT)
88     {
89         reason = BCM283X_I2C_REASON_ERROR_CLKT;
90     }
91     else if (remaining)
92     {
93         reason = BCM283X_I2C_REASON_ERROR_DATA;
94     }
95     BCM283X_BSC_C(base) |= (BSC_S_DONE & BSC_S_DONE);
96 
97     return reason;
98 }
99 
100 struct raspi_i2c_hw_config
101 {
102     rt_uint8_t bsc_num;
103     rt_uint8_t sdl_pin;
104     rt_uint8_t scl_pin;
105     rt_uint8_t sdl_mode;
106     rt_uint8_t scl_mode;
107 };
108 
109 #if (defined(BSP_USING_I2C0) || defined(BSP_USING_I2C1))
110 
111 static rt_ssize_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
112                                     struct rt_i2c_msg msgs[],
113                                     rt_uint32_t num);
114 static rt_ssize_t raspi_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
115                                     struct rt_i2c_msg msgs[],
116                                     rt_uint32_t num);
117 static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus,
118                                       int cmd,
119                                       void *args);
120 
121 static rt_uint32_t i2c_byte_wait_us = 0;
raspi_i2c_mst_xfer(struct rt_i2c_bus_device * bus,struct rt_i2c_msg msgs[],rt_uint32_t num)122 static rt_ssize_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
123                                     struct rt_i2c_msg msgs[],
124                                     rt_uint32_t num)
125 {
126     rt_size_t i;
127     rt_uint8_t reason;
128     RT_ASSERT(bus != RT_NULL);
129 
130     volatile rt_base_t base = (volatile rt_base_t)(bus->parent.user_data);
131 
132     if (bus->parent.user_data == 0)
133         base = BCM283X_BSC0_BASE;
134     else
135         base = BCM283X_BSC1_BASE;
136 
137     BCM283X_BSC_A(base) = msgs->addr;
138 
139     for (i = 0; i < num; i++)
140     {
141         if (msgs[i].flags & RT_I2C_RD)
142             reason = i2c_read_or_write(base, msgs->buf, msgs->len, 1);
143         else
144             reason = i2c_read_or_write(base, msgs->buf, msgs->len, 0);
145     }
146     return (reason == 0)? i : 0;
147 }
148 
raspi_i2c_slv_xfer(struct rt_i2c_bus_device * bus,struct rt_i2c_msg msgs[],rt_uint32_t num)149 static rt_ssize_t raspi_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
150                                     struct rt_i2c_msg msgs[],
151                                     rt_uint32_t num)
152 {
153     return 0;
154 }
raspi_i2c_bus_control(struct rt_i2c_bus_device * bus,int cmd,void * args)155 static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus,
156                                       int cmd,
157                                       void *args)
158 {
159     return RT_EOK;
160 }
161 
162 static const struct rt_i2c_bus_device_ops raspi_i2c_ops =
163 {
164     .master_xfer = raspi_i2c_mst_xfer,
165     .slave_xfer = raspi_i2c_slv_xfer,
166     .i2c_bus_control = raspi_i2c_bus_control,
167 };
168 
169 
raspi_i2c_configure(struct raspi_i2c_hw_config * cfg)170 static rt_err_t raspi_i2c_configure(struct raspi_i2c_hw_config *cfg)
171 {
172     RT_ASSERT(cfg != RT_NULL);
173 
174     volatile rt_uint32_t base = cfg->scl_mode ? BCM283X_BSC1_BASE : BCM283X_BSC0_BASE;
175 
176     GPIO_FSEL(cfg->sdl_pin, cfg->sdl_mode); /* SDA */
177     GPIO_FSEL(cfg->scl_pin, cfg->scl_mode); /* SCL */
178     /* use 0xFFFE mask to limit a max value and round down any odd number */
179     rt_uint32_t divider = (BCM283X_CORE_CLK_HZ / 10000) & 0xFFFE;
180     BCM283X_BSC_DIV(base) = (rt_uint16_t) divider;
181     i2c_byte_wait_us = (divider * 1000000 * 9 / BCM283X_CORE_CLK_HZ);
182 
183     return RT_EOK;
184 }
185 #endif
186 
187 #if defined (BSP_USING_I2C0)
188 #define I2C0_BUS_NAME    "i2c0"
189 static struct raspi_i2c_hw_config hw_device0 =
190 {
191     .bsc_num = 0,
192     .sdl_pin = RPI_GPIO_P1_27,
193     .scl_pin = RPI_GPIO_P1_28,
194     .sdl_mode = BCM283X_GPIO_FSEL_ALT0,
195     .scl_mode = BCM283X_GPIO_FSEL_ALT0,
196 };
197 
198 struct rt_i2c_bus_device device0 =
199 {
200     .ops = &raspi_i2c_ops,
201 };
202 
203 #endif
204 
205 #if defined (BSP_USING_I2C1)
206 #define I2C1_BUS_NAME    "i2c1"
207 static struct raspi_i2c_hw_config hw_device1 =
208 {
209     .bsc_num = 1,
210     .sdl_pin = RPI_GPIO_P1_03,
211     .scl_pin = RPI_GPIO_P1_05,
212     .sdl_mode = BCM283X_GPIO_FSEL_ALT0,
213     .scl_mode = BCM283X_GPIO_FSEL_ALT0,
214 };
215 struct rt_i2c_bus_device device1 =
216 {
217     .ops = &raspi_i2c_ops,
218 };
219 
220 #endif
221 
rt_hw_i2c_init(void)222 int rt_hw_i2c_init(void)
223 {
224 #if defined(BSP_USING_I2C0)
225     device0.parent.user_data = (void *)0;
226     raspi_i2c_configure(&hw_device0);
227     rt_i2c_bus_device_register(&device0, I2C0_BUS_NAME);
228 #endif
229 
230 #if defined(BSP_USING_I2C1)
231     device1.parent.user_data = (void *)1;
232     raspi_i2c_configure(&hw_device1);
233     rt_i2c_bus_device_register(&device1, I2C1_BUS_NAME);
234 #endif
235 
236     return 0;
237 }
238 INIT_DEVICE_EXPORT(rt_hw_i2c_init);
239