1 /* 2 * File : drv_sdio.h 3 * Copyright (c) 2006-2021, RT-Thread Development Team 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 * 7 * Change Logs: 8 * Date Author Notes 9 * 2019-07-29 zdzn first version 10 */ 11 12 #ifndef __DRV_SDIO_H__ 13 #define __DRV_SDIO_H__ 14 15 #include <rtthread.h> 16 #include <rtdevice.h> 17 #include <drivers/dev_mmcsd_core.h> 18 19 #include "board.h" 20 21 #define MMC0_BASE_ADDR 0x3F300000 22 23 /* Struct for Intrrrupt Information */ 24 #define SDXC_CmdDone BIT(0) 25 #define SDXC_DataDone BIT(1) 26 #define SDXC_BlockGap BIT(2) 27 #define SDXC_WriteRdy BIT(4) 28 #define SDXC_ReadRdy BIT(5) 29 #define SDXC_Card BIT(8) 30 #define SDXC_Retune BIT(12) 31 #define SDXC_BootAck BIT(13) 32 #define SDXC_EndBoot BIT(14) 33 #define SDXC_Err BIT(15) 34 #define SDXC_CTOErr BIT(16) 35 #define SDXC_CCRCErr BIT(17) 36 #define SDXC_CENDErr BIT(18) 37 #define SDXC_CBADErr BIT(19) 38 #define SDXC_DTOErr BIT(20) 39 #define SDXC_DCRCErr BIT(21) 40 #define SDXC_DENDErr BIT(22) 41 #define SDXC_ACMDErr BIT(24) 42 43 #define SDXC_BLKCNT_EN BIT(1) 44 #define SDXC_AUTO_CMD12_EN BIT(2) 45 #define SDXC_AUTO_CMD23_EN BIT(3) 46 #define SDXC_DAT_DIR BIT(4) //from card to host 47 #define SDXC_MULTI_BLOCK BIT(5) 48 #define SDXC_CMD_RSPNS_136 BIT(16) 49 #define SDXC_CMD_RSPNS_48 BIT(17) 50 #define SDXC_CMD_RSPNS_48busy BIT(16)|BIT(17) 51 #define SDXC_CHECK_CRC_CMD BIT(19) 52 #define SDXC_CMD_IXCHK_EN BIT(20) 53 #define SDXC_CMD_ISDATA BIT(21) 54 #define SDXC_CMD_SUSPEND BIT(22) 55 #define SDXC_CMD_RESUME BIT(23) 56 #define SDXC_CMD_ABORT BIT(23)|BIT(22) 57 58 #define SDXC_CMD_INHIBIT BIT(0) 59 #define SDXC_DAT_INHIBIT BIT(1) 60 #define SDXC_DAT_ACTIVE BIT(2) 61 #define SDXC_WRITE_TRANSFER BIT(8) 62 #define SDXC_READ_TRANSFER BIT(9) 63 64 struct sdhci_cmd_t 65 { 66 rt_uint32_t cmdidx; 67 rt_uint32_t cmdarg; 68 rt_uint32_t resptype; 69 rt_uint32_t datarw; 70 #define DATA_READ 1 71 #define DATA_WRITE 2 72 rt_uint32_t response[4]; 73 }; 74 75 struct sdhci_data_t 76 { 77 rt_uint8_t * buf; 78 rt_uint32_t flag; 79 rt_uint32_t blksz; 80 rt_uint32_t blkcnt; 81 }; 82 83 struct sdhci_t 84 { 85 char * name; 86 rt_uint32_t voltages; 87 rt_uint32_t width; 88 rt_uint32_t clock; 89 rt_err_t removeable; 90 void * sdcard; 91 92 rt_err_t (*detect)(struct sdhci_t * sdhci); 93 rt_err_t (*setwidth)(struct sdhci_t * sdhci, rt_uint32_t width); 94 rt_err_t (*setclock)(struct sdhci_t * sdhci, rt_uint32_t clock); 95 rt_err_t (*transfer)(struct sdhci_t * sdhci, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat); 96 void * priv; 97 }; 98 99 struct sdhci_pdata_t 100 { 101 rt_uint32_t virt; 102 }; 103 104 // EMMC command flags 105 #define CMD_TYPE_NORMAL 0x00000000 106 #define CMD_TYPE_SUSPEND 0x00400000 107 #define CMD_TYPE_RESUME 0x00800000 108 #define CMD_TYPE_ABORT 0x00c00000 109 #define CMD_IS_DATA 0x00200000 110 #define CMD_IXCHK_EN 0x00100000 111 #define CMD_CRCCHK_EN 0x00080000 112 #define CMD_RSPNS_NO 0x00000000 113 #define CMD_RSPNS_136 0x00010000 114 #define CMD_RSPNS_48 0x00020000 115 #define CMD_RSPNS_48B 0x00030000 116 #define TM_MULTI_BLOCK 0x00000020 117 #define TM_DAT_DIR_HC 0x00000000 118 #define TM_DAT_DIR_CH 0x00000010 119 #define TM_AUTO_CMD23 0x00000008 120 #define TM_AUTO_CMD12 0x00000004 121 #define TM_BLKCNT_EN 0x00000002 122 #define TM_MULTI_DATA (CMD_IS_DATA|TM_MULTI_BLOCK|TM_BLKCNT_EN) 123 124 #define RCA_NO 1 125 #define RCA_YES 2 126 127 // INTERRUPT register settings 128 #define INT_AUTO_ERROR 0x01000000 129 #define INT_DATA_END_ERR 0x00400000 130 #define INT_DATA_CRC_ERR 0x00200000 131 #define INT_DATA_TIMEOUT 0x00100000 132 #define INT_INDEX_ERROR 0x00080000 133 #define INT_END_ERROR 0x00040000 134 #define INT_CRC_ERROR 0x00020000 135 #define INT_CMD_TIMEOUT 0x00010000 136 #define INT_ERR 0x00008000 137 #define INT_ENDBOOT 0x00004000 138 #define INT_BOOTACK 0x00002000 139 #define INT_RETUNE 0x00001000 140 #define INT_CARD 0x00000100 141 #define INT_READ_RDY 0x00000020 142 #define INT_WRITE_RDY 0x00000010 143 #define INT_BLOCK_GAP 0x00000004 144 #define INT_DATA_DONE 0x00000002 145 #define INT_CMD_DONE 0x00000001 146 #define INT_ERROR_MASK (INT_CRC_ERROR|INT_END_ERROR|INT_INDEX_ERROR| \ 147 INT_DATA_TIMEOUT|INT_DATA_CRC_ERR|INT_DATA_END_ERR| \ 148 INT_ERR|INT_AUTO_ERROR) 149 #define INT_ALL_MASK (INT_CMD_DONE|INT_DATA_DONE|INT_READ_RDY|INT_WRITE_RDY|INT_ERROR_MASK) 150 151 #define EMMC_ARG2 (0x00) 152 #define EMMC_BLKSIZECNT (0x04) 153 #define EMMC_ARG1 (0x08) 154 #define EMMC_CMDTM (0x0c) 155 #define EMMC_RESP0 (0x10) 156 #define EMMC_RESP1 (0x14) 157 #define EMMC_RESP2 (0x18) 158 #define EMMC_RESP3 (0x1c) 159 #define EMMC_DATA (0x20) 160 #define EMMC_STATUS (0x24) 161 #define EMMC_CONTROL0 (0x28) 162 #define EMMC_CONTROL1 (0x2c) 163 #define EMMC_INTERRUPT (0x30) 164 #define EMMC_IRPT_MASK (0x34) 165 #define EMMC_IRPT_EN (0x38) 166 #define EMMC_CONTROL2 (0x3c) 167 #define EMMC_BOOT_TIMEOUT (0x70) 168 #define EMMC_EXRDFIFO_EN (0x84) 169 #define EMMC_SPI_INT_SPT (0xf0) 170 #define EMMC_SLOTISR_VER (0xfc) 171 172 // CONTROL register settings 173 #define C0_SPI_MODE_EN 0x00100000 174 #define C0_HCTL_HS_EN 0x00000004 175 #define C0_HCTL_DWITDH 0x00000002 176 177 #define C1_SRST_DATA 0x04000000 178 #define C1_SRST_CMD 0x02000000 179 #define C1_SRST_HC 0x01000000 180 #define C1_TOUNIT_DIS 0x000f0000 181 #define C1_TOUNIT_MAX 0x000e0000 182 #define C1_CLK_GENSEL 0x00000020 183 #define C1_CLK_EN 0x00000004 184 #define C1_CLK_STABLE 0x00000002 185 #define C1_CLK_INTLEN 0x00000001 186 187 #define FREQ_SETUP 400000 // 400 Khz 188 #define FREQ_NORMAL 25000000 // 25 Mhz 189 190 // SLOTISR_VER values 191 #define HOST_SPEC_NUM 0x00ff0000 192 #define HOST_SPEC_NUM_SHIFT 16 193 #define HOST_SPEC_V3 2 194 #define HOST_SPEC_V2 1 195 #define HOST_SPEC_V1 0 196 197 // STATUS register settings 198 #define SR_DAT_LEVEL1 0x1e000000 199 #define SR_CMD_LEVEL 0x01000000 200 #define SR_DAT_LEVEL0 0x00f00000 201 #define SR_DAT3 0x00800000 202 #define SR_DAT2 0x00400000 203 #define SR_DAT1 0x00200000 204 #define SR_DAT0 0x00100000 205 #define SR_WRITE_PROT 0x00080000 // From SDHC spec v2, BCM says reserved 206 #define SR_READ_AVAILABLE 0x00000800 // ???? undocumented 207 #define SR_WRITE_AVAILABLE 0x00000400 // ???? undocumented 208 #define SR_READ_TRANSFER 0x00000200 209 #define SR_WRITE_TRANSFER 0x00000100 210 #define SR_DAT_ACTIVE 0x00000004 211 #define SR_DAT_INHIBIT 0x00000002 212 #define SR_CMD_INHIBIT 0x00000001 213 214 #define CONFIG_MMC_USE_DMA 215 #define DMA_ALIGN (32U) 216 217 #define SD_CMD_INDEX(a) ((a) << 24) 218 #define SD_CMD_RESERVED(a) 0xffffffff 219 #define SD_CMD_INDEX(a) ((a) << 24) 220 #define SD_CMD_TYPE_NORMAL 0x0 221 #define SD_CMD_TYPE_SUSPEND (1 << 22) 222 #define SD_CMD_TYPE_RESUME (2 << 22) 223 #define SD_CMD_TYPE_ABORT (3 << 22) 224 #define SD_CMD_TYPE_MASK (3 << 22) 225 #define SD_CMD_ISDATA (1 << 21) 226 #define SD_CMD_IXCHK_EN (1 << 20) 227 #define SD_CMD_CRCCHK_EN (1 << 19) 228 #define SD_CMD_RSPNS_TYPE_NONE 0 // For no response 229 #define SD_CMD_RSPNS_TYPE_136 (1 << 16) // For response R2 (with CRC), R3,4 (no CRC) 230 #define SD_CMD_RSPNS_TYPE_48 (2 << 16) // For responses R1, R5, R6, R7 (with CRC) 231 #define SD_CMD_RSPNS_TYPE_48B (3 << 16) // For responses R1b, R5b (with CRC) 232 #define SD_CMD_RSPNS_TYPE_MASK (3 << 16) 233 #define SD_CMD_MULTI_BLOCK (1 << 5) 234 #define SD_CMD_DAT_DIR_HC 0 235 #define SD_CMD_DAT_DIR_CH (1 << 4) 236 #define SD_CMD_AUTO_CMD_EN_NONE 0 237 #define SD_CMD_AUTO_CMD_EN_CMD12 (1 << 2) 238 #define SD_CMD_AUTO_CMD_EN_CMD23 (2 << 2) 239 #define SD_CMD_BLKCNT_EN (1 << 1) 240 #define SD_CMD_DMA 1 241 #define SD_RESP_NONE SD_CMD_RSPNS_TYPE_NONE 242 #define SD_RESP_R1 (SD_CMD_RSPNS_TYPE_48) // | SD_CMD_CRCCHK_EN) 243 #define SD_RESP_R1b (SD_CMD_RSPNS_TYPE_48B) // | SD_CMD_CRCCHK_EN) 244 #define SD_RESP_R2 (SD_CMD_RSPNS_TYPE_136) //| SD_CMD_CRCCHK_EN) 245 #define SD_RESP_R3 SD_CMD_RSPNS_TYPE_48 246 #define SD_RESP_R4 SD_CMD_RSPNS_TYPE_136 247 #define SD_RESP_R5 (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN) 248 #define SD_RESP_R5b (SD_CMD_RSPNS_TYPE_48B | SD_CMD_CRCCHK_EN) 249 #define SD_RESP_R6 (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN) 250 #define SD_RESP_R7 (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN) 251 #define SD_DATA_READ (SD_CMD_ISDATA | SD_CMD_DAT_DIR_CH) 252 #define SD_DATA_WRITE (SD_CMD_ISDATA | SD_CMD_DAT_DIR_HC) 253 #endif 254