1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2020-12-02 bigmagic first version
9 */
10 #include "drv_dma.h"
11 #include "raspi4.h"
12 #include <rtthread.h>
13
14 volatile unsigned int __attribute__((aligned(256))) dma_disc[32];
15 //https://www.raspberrypi.org/forums/viewtopic.php?f=72&t=10276
16 static struct rt_semaphore dma_sem;
17
18 //DMA 0 1 2 3 4 5 6
19 typedef struct _dma_ctrl_block
20 {
21 unsigned int TI; // Transfer information
22 unsigned int SOURCE_AD; // source address
23 unsigned int DEST_AD; // destination address
24 unsigned int TXFR_LEN; // transfer length
25 unsigned int STRIDE; // 2D mode stride
26 struct _dma_ctrl_block *NEXTCONBK; // Next control block address
27 unsigned int DEBUG;
28 unsigned int reserved1;
29
30 } dma_ctrl_block_t;
31
32 //DMA 7 8 9 10
33 typedef struct _dma_lite_ctrl_block
34 {
35 unsigned int TI; // Transfer information
36 unsigned int SOURCE_AD; // source address
37 unsigned int DEST_AD; // destination address
38 unsigned int TXFR_LEN; // transfer length
39 struct _dma_lite_ctrl_block *NEXTCONBK; // Next control block address
40 unsigned int DEBUG;
41 unsigned int reserved1;
42 unsigned int reserved2;
43
44 } dma_lite_ctrl_block_t;
45
46 //DMA 11 12 13 14 15
47 typedef struct _dma4_ctrl_block
48 {
49 unsigned int TI; // Transfer information
50 unsigned int SOURCE_AD0; // source address0
51 unsigned int SOURCE_AD1; // source address1
52 unsigned int DEST_AD0; // destination address0
53 unsigned int DEST_AD1; // destination address1
54 unsigned int TXFR_LEN; // transfer length
55 unsigned int STRIDE; // 2D mode stride
56 struct _dma4_ctrl_block *NEXTCONBK; // Next control block address
57 } dma4_ctrl_block_t;
58
59 static dma_lite_ctrl_block_t *ctr_blocks;
60
dma_irq(int irq,void * param)61 static void dma_irq(int irq, void *param)
62 {
63 if (DMA_INT_STATUS_REG & DMA_INT7)
64 {
65 DMA_CS(7) = DMA_CS_INT;
66 rt_sem_release(&dma_sem);
67 }
68 }
69
70 //dma 7 8 9 10:XLENGTH
dma_memcpy(void * src,void * dst,unsigned int size,unsigned int dch,unsigned int timeout)71 rt_err_t dma_memcpy(void *src, void *dst, unsigned int size, unsigned int dch, unsigned int timeout)
72 {
73 rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, dst, size);
74
75 /* Stop DMA, if it was already started */
76 DMA_CS(dch) = DMA_CS_RESET;
77
78 /* Clear DMA status flags */
79 DMA_CS(dch) = DMA_CS_INT | DMA_CS_END; /* Interrupted flag & Transmission ended flag*/
80 //cb info
81 ctr_blocks->TI = DMA_TI_SRC_INC | DMA_TI_DEST_INC | DMA_TI_INTEN;
82 ctr_blocks->SOURCE_AD = (unsigned int)src;
83 ctr_blocks->DEST_AD = (unsigned int)dst;
84 ctr_blocks->TXFR_LEN = size;
85 ctr_blocks->NEXTCONBK = 0;
86 ctr_blocks->reserved1 = 0;
87 ctr_blocks->reserved2 = 0;
88
89 rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, ctr_blocks, sizeof(dma_lite_ctrl_block_t) * 8);
90
91 DMA_CONBLK_AD(dch) = (rt_uint32_t)ctr_blocks;
92 DMA_CS(dch) = DMA_CS_INT | DMA_CS_END | DMA_CS_ACTIVE;
93
94 if(rt_sem_take(&dma_sem, timeout) != RT_EOK)
95 {
96 rt_kprintf("dma transfer timeout!\n");
97 return -RT_ERROR;
98 }
99
100 return RT_EOK;
101 }
102
dma_init(unsigned char dch)103 void dma_init(unsigned char dch)
104 {
105 rt_sem_init(&dma_sem, "dma_sem", 0, RT_IPC_FLAG_FIFO);
106
107 ctr_blocks = (dma_lite_ctrl_block_t *)&dma_disc[0]; //rt_malloc(sizeof(DMA_Lite_Control_Block));
108 //Make sure DMA channel is enabled by
109 //writing the corresponding bit in DMA_ENABLE in the DMA register to 1
110 DMA_ENABLE_REG = (1 << dch);
111
112 rt_hw_interrupt_install(IRQ_DMA7_DMA8, dma_irq, RT_NULL, "dma_irq");
113 rt_hw_interrupt_umask(IRQ_DMA7_DMA8);
114 }
115