1 2 /* 3 * Copyright (c) 2006-2020, RT-Thread Development Team 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 * 7 * Change Logs: 8 * Date Author Notes 9 * 2020-10-30 bigmagic first version 10 */ 11 12 #ifndef __DRV_ETH_H__ 13 #define __DRV_ETH_H__ 14 15 16 //#define BIT(nr) (1UL << (nr)) 17 #define ENET_FRAME_MAX_FRAMELEN 1518U 18 19 #define SYS_REV_CTRL (0x00) 20 #define SYS_PORT_CTRL (0x04) 21 #define PORT_MODE_EXT_GPHY (3) 22 23 #define GENET_SYS_OFF (0x0000) 24 #define SYS_RBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x08) 25 #define SYS_TBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x0c) 26 27 #define GENET_EXT_OFF (0x0080) 28 #define EXT_RGMII_OOB_CTRL (GENET_EXT_OFF + 0x0c) 29 #define RGMII_LINK BIT(4) 30 #define OOB_DISABLE BIT(5) 31 #define RGMII_MODE_EN BIT(6) 32 #define ID_MODE_DIS BIT(16) 33 34 #define GENET_RBUF_OFF (0x0300) 35 #define RBUF_TBUF_SIZE_CTRL (GENET_RBUF_OFF + 0xb4) 36 #define RBUF_CTRL (GENET_RBUF_OFF + 0x00) 37 #define RBUF_ALIGN_2B BIT(1) 38 39 #define GENET_UMAC_OFF (0x0800) 40 #define UMAC_MIB_CTRL (GENET_UMAC_OFF + 0x580) 41 #define UMAC_MAX_FRAME_LEN (GENET_UMAC_OFF + 0x014) 42 #define UMAC_MAC0 (GENET_UMAC_OFF + 0x00c) 43 #define UMAC_MAC1 (GENET_UMAC_OFF + 0x010) 44 #define UMAC_CMD (GENET_UMAC_OFF + 0x008) 45 #define MDIO_CMD (GENET_UMAC_OFF + 0x614) 46 #define UMAC_TX_FLUSH (GENET_UMAC_OFF + 0x334) 47 #define MDIO_START_BUSY BIT(29) 48 #define MDIO_READ_FAIL BIT(28) 49 #define MDIO_RD (2 << 26) 50 #define MDIO_WR BIT(26) 51 #define MDIO_PMD_SHIFT (21) 52 #define MDIO_PMD_MASK (0x1f) 53 #define MDIO_REG_SHIFT (16) 54 #define MDIO_REG_MASK (0x1f) 55 56 #define GENET_INTRL2_OFF (0x0200) 57 #define GENET_INTRL2_CPU_STAT (GENET_INTRL2_OFF + 0x00) 58 #define GENET_INTRL2_CPU_CLEAR (GENET_INTRL2_OFF + 0x08) 59 #define GENET_INTRL2_CPU_STAT_MASK (GENET_INTRL2_OFF + 0x0c) 60 #define GENET_INTRL2_CPU_SET_MASK (GENET_INTRL2_OFF + 0x10) 61 #define GENET_INTRL2_CPU_CLEAR_MASK (GENET_INTRL2_OFF + 0x14) 62 #define GENET_IRQ_MDIO_ERROR BIT(24) 63 #define GENET_IRQ_MDIO_DONE BIT(23) 64 #define GENET_IRQ_TXDMA_DONE BIT(16) 65 #define GENET_IRQ_RXDMA_DONE BIT(13) 66 67 #define CMD_TX_EN BIT(0) 68 #define CMD_RX_EN BIT(1) 69 #define UMAC_SPEED_10 (0) 70 #define UMAC_SPEED_100 (1) 71 #define UMAC_SPEED_1000 (2) 72 #define UMAC_SPEED_2500 (3) 73 #define CMD_SPEED_SHIFT (2) 74 #define CMD_SPEED_MASK (3) 75 #define CMD_SW_RESET BIT(13) 76 #define CMD_LCL_LOOP_EN BIT(15) 77 #define CMD_TX_EN BIT(0) 78 #define CMD_RX_EN BIT(1) 79 80 #define MIB_RESET_RX BIT(0) 81 #define MIB_RESET_RUNT BIT(1) 82 #define MIB_RESET_TX BIT(2) 83 84 /* total number of Buffer Descriptors, same for Rx/Tx */ 85 #define TOTAL_DESCS (256) 86 #define RX_DESCS TOTAL_DESCS 87 #define TX_DESCS TOTAL_DESCS 88 89 #define DEFAULT_Q (0x10) 90 91 #define ETH_DATA_LEN (1500) 92 #define ETH_HLEN (14) 93 #define VLAN_HLEN (4) 94 #define ETH_FCS_LEN (4) 95 /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. 96 * 1536 is multiple of 256 bytes 97 */ 98 #define ENET_BRCM_TAG_LEN (6) 99 #define ENET_PAD (8) 100 #define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + \ 101 VLAN_HLEN + ENET_BRCM_TAG_LEN + \ 102 ETH_FCS_LEN + ENET_PAD) 103 104 /* Tx/Rx Dma Descriptor common bits */ 105 #define DMA_EN BIT(0) 106 #define DMA_RING_BUF_EN_SHIFT (0x01) 107 #define DMA_RING_BUF_EN_MASK (0xffff) 108 #define DMA_BUFLENGTH_MASK (0x0fff) 109 #define DMA_BUFLENGTH_SHIFT (16) 110 #define DMA_RING_SIZE_SHIFT (16) 111 #define DMA_OWN (0x8000) 112 #define DMA_EOP (0x4000) 113 #define DMA_SOP (0x2000) 114 #define DMA_WRAP (0x1000) 115 #define DMA_MAX_BURST_LENGTH (0x8) 116 /* Tx specific DMA descriptor bits */ 117 #define DMA_TX_UNDERRUN (0x0200) 118 #define DMA_TX_APPEND_CRC (0x0040) 119 #define DMA_TX_OW_CRC (0x0020) 120 #define DMA_TX_DO_CSUM (0x0010) 121 #define DMA_TX_QTAG_SHIFT (7) 122 123 /* DMA rings size */ 124 #define DMA_RING_SIZE (0x40) 125 #define DMA_RINGS_SIZE (DMA_RING_SIZE * (DEFAULT_Q + 1)) 126 127 /* DMA descriptor */ 128 #define DMA_DESC_LENGTH_STATUS (0x00) 129 #define DMA_DESC_ADDRESS_LO (0x04) 130 #define DMA_DESC_ADDRESS_HI (0x08) 131 #define DMA_DESC_SIZE (12) 132 133 #define GENET_RX_OFF (0x2000) 134 #define GENET_RDMA_REG_OFF \ 135 (GENET_RX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) 136 #define GENET_TX_OFF (0x4000) 137 #define GENET_TDMA_REG_OFF \ 138 (GENET_TX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) 139 140 #define DMA_FC_THRESH_HI (RX_DESCS >> 4) 141 #define DMA_FC_THRESH_LO (5) 142 #define DMA_FC_THRESH_VALUE ((DMA_FC_THRESH_LO << 16) | \ 143 DMA_FC_THRESH_HI) 144 145 #define DMA_XOFF_THRESHOLD_SHIFT (16) 146 147 #define TDMA_RING_REG_BASE \ 148 (GENET_TDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) 149 #define TDMA_READ_PTR (TDMA_RING_REG_BASE + 0x00) 150 #define TDMA_CONS_INDEX (TDMA_RING_REG_BASE + 0x08) 151 #define TDMA_PROD_INDEX (TDMA_RING_REG_BASE + 0x0c) 152 #define DMA_RING_BUF_SIZE (0x10) 153 #define DMA_START_ADDR (0x14) 154 #define DMA_END_ADDR (0x1c) 155 #define DMA_MBUF_DONE_THRESH (0x24) 156 #define TDMA_FLOW_PERIOD (TDMA_RING_REG_BASE + 0x28) 157 #define TDMA_WRITE_PTR (TDMA_RING_REG_BASE + 0x2c) 158 159 #define RDMA_RING_REG_BASE \ 160 (GENET_RDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) 161 #define RDMA_WRITE_PTR (RDMA_RING_REG_BASE + 0x00) 162 #define RDMA_PROD_INDEX (RDMA_RING_REG_BASE + 0x08) 163 #define RDMA_CONS_INDEX (RDMA_RING_REG_BASE + 0x0c) 164 #define RDMA_XON_XOFF_THRESH (RDMA_RING_REG_BASE + 0x28) 165 #define RDMA_READ_PTR (RDMA_RING_REG_BASE + 0x2c) 166 167 #define TDMA_REG_BASE (GENET_TDMA_REG_OFF + DMA_RINGS_SIZE) 168 #define RDMA_REG_BASE (GENET_RDMA_REG_OFF + DMA_RINGS_SIZE) 169 #define DMA_RING_CFG (0x00) 170 #define DMA_CTRL (0x04) 171 #define DMA_SCB_BURST_SIZE (0x0c) 172 173 #define RX_BUF_LENGTH (2048) 174 #define RX_TOTAL_BUFSIZE (RX_BUF_LENGTH * RX_DESCS) 175 #define RX_BUF_OFFSET (2) 176 177 #define PHY_INTERFACE_MODE_RGMII (7) 178 #define PHY_INTERFACE_MODE_RGMII_RXID (9) 179 180 #define BCM54213PE_MII_CONTROL (0x00) 181 #define BCM54213PE_MII_STATUS (0x01) 182 #define BCM54213PE_PHY_IDENTIFIER_HIGH (0x02) 183 #define BCM54213PE_PHY_IDENTIFIER_LOW (0x03) 184 185 #define BCM54213PE_AUTO_NEGOTIATION_ADV (0x04) 186 #define BCM54213PE_AUTO_NEGOTIATION_LINK (0x05) 187 #define BCM54213PE_AUTO_NEGOTIATION_EXPANSION (0x06) 188 189 #define BCM54213PE_NEXT_PAGE_TX (0x07) 190 191 #define BCM54213PE_PARTNER_RX (0x08) 192 193 #define BCM54213PE_CONTROL (0x09) 194 #define BCM54213PE_STATUS (0x0A) 195 196 #define BCM54213PE_IEEE_EXTENDED_STATUS (0x0F) 197 #define BCM54213PE_PHY_EXTENDED_CONTROL (0x10) 198 #define BCM54213PE_PHY_EXTENDED_STATUS (0x11) 199 200 #define BCM54213PE_RECEIVE_ERROR_COUNTER (0x12) 201 #define BCM54213PE_FALSE_C_S_COUNTER (0x13) 202 #define BCM54213PE_RECEIVE_NOT_OK_COUNTER (0x14) 203 204 #define BCM54213PE_VERSION_B1 (0x600d84a2) 205 #define BCM54213PE_VERSION_X (0x600d84a0) 206 207 //BCM54213PE_MII_CONTROL 208 #define MII_CONTROL_PHY_RESET (1 << 15) 209 #define MII_CONTROL_AUTO_NEGOTIATION_ENABLED (1 << 12) 210 #define MII_CONTROL_AUTO_NEGOTIATION_RESTART (1 << 9) 211 #define MII_CONTROL_PHY_FULL_DUPLEX (1 << 8) 212 #define MII_CONTROL_SPEED_SELECTION (1 << 6) 213 214 //BCM54213PE_MII_STATUS 215 #define MII_STATUS_LINK_UP (1 << 2) 216 217 //BCM54213PE_CONTROL 218 #define CONTROL_FULL_DUPLEX_CAPABILITY (1 << 9) 219 #define CONTROL_HALF_DUPLEX_CAPABILITY (1 << 8) 220 221 #define SPEED_1000 (1000) 222 #define SPEED_100 (100) 223 #define SPEED_10 (10) 224 225 #endif/* __DRV_ETH_H__ */ 226