1 /*
2 * Copyright (c) 2006-2020, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2020-06-22 bigmagic first version
9 */
10 #include <rtthread.h>
11 #include <rthw.h>
12 #include <rtdevice.h>
13
14 #include "raspi4.h"
15 #include "drv_spi.h"
16
17 #ifdef BSP_USING_SPI
18
19 #define RPI_CORE_CLK_HZ (250000000)
20 #define BSP_SPI_MAX_HZ (30* 1000 *1000)
21 #define SPITIMEOUT 0x0FFF
22
23 static rt_uint8_t raspi_byte_reverse_table[] =
24 {
25 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
26 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
27 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
28 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
29 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
30 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
31 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
32 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
33 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
34 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
35 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
36 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
37 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
38 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
39 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
40 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
41 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
42 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
43 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
44 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
45 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
46 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
47 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
48 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
49 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
50 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
51 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
52 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
53 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
54 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
55 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
56 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff
57 };
58
59 #if defined (BSP_USING_SPI0_BUS)
60 #define SPI0_BUS_NAME "spi0"
61 #define SPI0_DEVICE0_NAME "spi0.0"
62 #define SPI0_DEVICE1_NAME "spi0.1"
63
64 struct rt_spi_bus spi0_bus;
65
66 #if defined (BSP_USING_SPI0_DEVICE0)
67 static struct rt_spi_device spi0_device0;
68 #endif
69
70 #if defined (BSP_USING_SPI0_DEVICE1)
71 static struct rt_spi_device spi0_device1;
72 #endif
73 #endif
74
raspi_spi_configure(struct rt_spi_device * device,struct rt_spi_configuration * cfg)75 static rt_err_t raspi_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
76 {
77 RT_ASSERT(cfg != RT_NULL);
78 RT_ASSERT(device != RT_NULL);
79 rt_uint16_t divider;
80 struct raspi_spi_device* hw_config = (struct raspi_spi_device *)(device->parent.user_data);
81 struct raspi_spi_hw_config *hwcfg = (struct raspi_spi_hw_config *)hw_config->spi_hw_config;
82 // spi clear fifo
83 SPI_REG_CS(hwcfg->hw_base) = (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX);
84 if(cfg->mode & RT_SPI_CPOL)
85 {
86 SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CPOL;
87 }
88
89 if(cfg->mode & RT_SPI_CPHA)
90 {
91 SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CPHA;
92 }
93
94 if(cfg->mode & RT_SPI_CS_HIGH)
95 {
96 SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CSPOL_HIGH;
97 }
98
99 //set clk
100 if (cfg->max_hz > BSP_SPI_MAX_HZ)
101 cfg->max_hz = BSP_SPI_MAX_HZ;
102
103 divider = (rt_uint16_t) ((rt_uint32_t) RPI_CORE_CLK_HZ / cfg->max_hz);
104 divider &= 0xFFFE;
105
106 SPI_REG_CLK(hwcfg->hw_base) = divider;
107
108 return RT_EOK;
109 }
110
correct_order(rt_uint8_t b,rt_uint8_t flag)111 rt_uint8_t correct_order(rt_uint8_t b, rt_uint8_t flag)
112 {
113 if (flag)
114 return raspi_byte_reverse_table[b];//reverse
115 else
116 return b;
117 }
118
spi_transfernb(struct raspi_spi_hw_config * hwcfg,rt_uint8_t * tbuf,rt_uint8_t * rbuf,rt_uint32_t len,rt_uint8_t flag)119 static rt_err_t spi_transfernb(struct raspi_spi_hw_config *hwcfg, rt_uint8_t* tbuf, rt_uint8_t* rbuf, rt_uint32_t len, rt_uint8_t flag)
120 {
121 rt_uint32_t TXCnt=0;
122 rt_uint32_t RXCnt=0;
123
124 /* Clear TX and RX fifos */
125 SPI_REG_CS(hwcfg->hw_base) |= (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX);
126
127 /* Set TA = 1 */
128 SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_TA;
129
130 /* Use the FIFO's to reduce the interbyte times */
131 while ((TXCnt < len) || (RXCnt < len))
132 {
133 /* TX fifo not full, so add some more bytes */
134 while (((SPI_REG_CS(hwcfg->hw_base) & SPI_CS_TX_DATA)) && (TXCnt < len))
135 {
136 SPI_REG_FIFO(hwcfg->hw_base) = correct_order(tbuf[TXCnt],flag);
137 TXCnt++;
138 }
139 /* Rx fifo not empty, so get the next received bytes */
140 while (((SPI_REG_CS(hwcfg->hw_base) & SPI_CS_RX_DATA)) && (RXCnt < len))
141 {
142 rbuf[RXCnt] = correct_order(SPI_REG_FIFO(hwcfg->hw_base), flag);
143 RXCnt++;
144 }
145 }
146 /* Wait for DONE to be set */
147 while (!(SPI_REG_CS(hwcfg->hw_base) & SPI_CS_DONE));
148 /* Set TA = 0, and also set the barrier */
149 SPI_REG_CS(hwcfg->hw_base) |= (0 & SPI_CS_TA);
150
151 return RT_EOK;
152 }
153
raspi_spi_xfer(struct rt_spi_device * device,struct rt_spi_message * message)154 static rt_uint32_t raspi_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
155 {
156 rt_err_t res;
157 rt_uint8_t flag;
158 RT_ASSERT(device != RT_NULL);
159 RT_ASSERT(device->bus != RT_NULL);
160 RT_ASSERT(device->parent.user_data != RT_NULL);
161 RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL);
162
163 struct rt_spi_configuration config = device->config;
164 struct raspi_spi_device * hw_config = (struct raspi_spi_device *)device->parent.user_data;
165 GPIO_PIN cs_pin = (GPIO_PIN)hw_config->cs_pin;
166 struct raspi_spi_hw_config *hwcfg = (struct raspi_spi_hw_config *)hw_config->spi_hw_config;
167
168 if (config.mode & RT_SPI_MSB)
169 {
170 flag = 0;
171 }
172 else
173 {
174 flag = 1;
175 }
176
177 if (message->cs_take)
178 {
179 (config.mode & RT_SPI_CS_HIGH)?prev_raspi_pin_write(cs_pin, 1):prev_raspi_pin_write(cs_pin, 0);
180 }
181
182 res = spi_transfernb(hwcfg, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, flag);
183 if (message->cs_release)
184 {
185 (config.mode & RT_SPI_CS_HIGH)?prev_raspi_pin_write(cs_pin, 0):prev_raspi_pin_write(cs_pin, 1);
186 }
187 if (res != RT_EOK)
188 return -RT_ERROR;
189
190 return message->length;
191 }
192
raspi_spi_bus_attach_device(const char * bus_name,struct raspi_spi_device * device)193 rt_err_t raspi_spi_bus_attach_device(const char *bus_name, struct raspi_spi_device *device)
194 {
195 rt_err_t ret;
196 RT_ASSERT(device != RT_NULL);
197 ret = rt_spi_bus_attach_device(device->spi_device, device->device_name, bus_name, (void *)(device));
198 return ret;
199 }
200
raspi_spi_hw_init(struct raspi_spi_hw_config * hwcfg)201 rt_err_t raspi_spi_hw_init(struct raspi_spi_hw_config *hwcfg)
202 {
203 prev_raspi_pin_mode(hwcfg->sclk_pin, hwcfg->sclk_mode);
204 prev_raspi_pin_mode(hwcfg->miso_pin, hwcfg->miso_mode);
205 prev_raspi_pin_mode(hwcfg->mosi_pin, hwcfg->mosi_mode);
206 #if defined (BSP_USING_SPI0_DEVICE0)
207 prev_raspi_pin_mode(hwcfg->ce0_pin, hwcfg->ce0_mode);
208 #endif
209
210 #if defined (BSP_USING_SPI0_DEVICE1)
211 prev_raspi_pin_mode(hwcfg->ce1_pin, hwcfg->ce1_mode);
212 #endif
213 //clear rx and tx
214 SPI_REG_CS(hwcfg->hw_base) = (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX);
215 //enable chip select
216 #if defined (BSP_USING_SPI0_DEVICE0)
217 SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CHIP_SELECT_0;
218 #endif
219
220 #if defined (BSP_USING_SPI0_DEVICE1)
221 SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CHIP_SELECT_1;
222 #endif
223
224 #if defined (BSP_USING_SPI0_DEVICE0) && defined (BSP_USING_SPI0_DEVICE1)
225 HWREG32(SPI_REG_CS(hwcfg->hw_base)) |= (SPI_CS_CHIP_SELECT_0 | SPI_CS_CHIP_SELECT_1);
226 #endif
227 return RT_EOK;
228 }
229
230 static struct rt_spi_ops raspi_spi_ops =
231 {
232 .configure = raspi_spi_configure,
233 .xfer = raspi_spi_xfer
234 };
235
236 struct raspi_spi_hw_config raspi_spi0_hw =
237 {
238 .spi_num = 0,
239 .sclk_pin = GPIO_PIN_11,
240 .sclk_mode = ALT0,
241 .mosi_pin = GPIO_PIN_10,
242 .mosi_mode = ALT0,
243 .miso_pin = GPIO_PIN_9,
244 .miso_mode = ALT0,
245
246 #if defined (BSP_USING_SPI0_DEVICE0)
247 .ce0_pin = GPIO_PIN_8,
248 .ce0_mode = ALT0,
249 #endif
250
251 #if defined (BSP_USING_SPI0_DEVICE1)
252 .ce1_pin = GPIO_PIN_7,
253 .ce1_mode = ALT0,
254 #endif
255 .hw_base = SPI_0_BASE,
256 };
257 #endif
258
259 #if defined (BSP_USING_SPI0_DEVICE0)
260 struct raspi_spi_device raspi_spi0_device0 =
261 {
262 .device_name = SPI0_DEVICE0_NAME,
263 .spi_bus = &spi0_bus,
264 .spi_device = &spi0_device0,
265 .spi_hw_config = &raspi_spi0_hw,
266 .cs_pin = GPIO_PIN_8,
267 };
268 #endif
269
270 #if defined (BSP_USING_SPI0_DEVICE1)
271 struct raspi_spi_device raspi_spi0_device1 =
272 {
273 .device_name = SPI0_DEVICE1_NAME,
274 .spi_bus = &spi0_bus,
275 .spi_device = &spi0_device1,
276 .cs_pin = GPIO_PIN_7,
277 };
278 #endif
279
rt_hw_spi_init(void)280 int rt_hw_spi_init(void)
281 {
282 #if defined (BSP_USING_SPI0_BUS)
283 raspi_spi_hw_init(&raspi_spi0_hw);
284 rt_spi_bus_register(&spi0_bus, SPI0_BUS_NAME, &raspi_spi_ops);
285
286 #if defined (BSP_USING_SPI0_DEVICE0)
287 raspi_spi_bus_attach_device(SPI0_BUS_NAME, &raspi_spi0_device0);
288 #endif
289
290 #if defined (BSP_USING_SPI0_DEVICE1)
291 raspi_spi_bus_attach_device(SPI0_BUS_NAME, &raspi_spi0_device1);
292 #endif
293 #endif
294 return RT_EOK;
295 }
296 INIT_DEVICE_EXPORT(rt_hw_spi_init);
297