1 /*
2 * Copyright (c) 2006-2023, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2023-02-06 RT-Thread first version
9 */
10 #ifndef __RASPI4_H__
11 #define __RASPI4_H__
12
13 #include <rtthread.h>
14
15 //https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/rpi_DATA_2711_1p0.pdf
16
17 #define __REG32(x) (*((volatile unsigned int *)(x)))
18 #define __REG16(x) (*((volatile unsigned short *)(x)))
19
20 /* GIC IRQ MAX */
21 #define MAX_HANDLERS (256)
22
23 /* base address */
24 #define PER_BASE (0xFE000000)
25
26 //gpio offset
27 #define GPIO_BASE_OFFSET (0x00200000)
28
29
30 #define PL011_UART_BASE_OFFSET (0x00201000)
31 //pl011 offset
32 #define PL011_UART0_BASE_OFFSET (0x00201000)
33 #define PL011_UART2_BASE_OFFSET (0x00201400)
34 #define PL011_UART3_BASE_OFFSET (0x00201600)
35 #define PL011_UART4_BASE_OFFSET (0x00201800)
36 #define PL011_UART5_BASE_OFFSET (0x00201A00)
37
38 //pactl cs offset
39 #define PACTL_CS_OFFSET (0x00204E00)
40
41 //aux offset
42 #define AUX_BASE_OFFSET (0x00215000)
43
44 /* GPIO */
45 #define GPIO_BASE_ADDR (PER_BASE + GPIO_BASE_OFFSET)
46 extern size_t gpio_base_addr;
47 #define GPIO_BASE (gpio_base_addr)
48 #define GPIO_IRQ_NUM (3) //40 pin mode
49 #define IRQ_GPIO0 (96 + 49) //bank0 (0 to 27)
50 #define IRQ_GPIO1 (96 + 50) //bank1 (28 to 45)
51 #define IRQ_GPIO2 (96 + 51) //bank2 (46 to 57)
52 #define IRQ_GPIO3 (96 + 52) //bank3
53
54 /* Timer (ARM side) */
55 #define ARM_TIMER_IRQ (64)
56 extern size_t arm_timer_base;
57 #define ARM_TIMER_BASE (PER_BASE + 0xB000)
58 #define ARM_TIMER_LOAD HWREG32(arm_timer_base + 0x400)
59 #define ARM_TIMER_VALUE HWREG32(arm_timer_base + 0x404)
60 #define ARM_TIMER_CTRL HWREG32(arm_timer_base + 0x408)
61 #define ARM_TIMER_IRQCLR HWREG32(arm_timer_base + 0x40C)
62 #define ARM_TIMER_RAWIRQ HWREG32(arm_timer_base + 0x410)
63 #define ARM_TIMER_MASKIRQ HWREG32(arm_timer_base + 0x414)
64 #define ARM_TIMER_RELOAD HWREG32(arm_timer_base + 0x418)
65 #define ARM_TIMER_PREDIV HWREG32(arm_timer_base + 0x41C)
66 #define ARM_TIMER_CNTR HWREG32(arm_timer_base + 0x420)
67
68 /* UART PL011 */
69 #define UART_BASE (PER_BASE + PL011_UART_BASE_OFFSET)
70 //extern uint32_t uart_base_addr;
71 #define UART0_BASE (UART_BASE + 0x0)
72 #define UART2_BASE (UART_BASE + 0x400)
73 #define UART3_BASE (UART_BASE + 0x600)
74 #define UART4_BASE (UART_BASE + 0x800)
75 #define UART5_BASE (UART_BASE + 0xA00)
76 #define IRQ_AUX_UART (96 + 29)
77 #define UART_REFERENCE_CLOCK (48000000)
78
79 /* AUX */
80 //#define AUX_BASE_ADDR (PER_BASE + AUX_BASE_OFFSET)
81 //extern uint32_t aux_addr;
82 //#define AUX_BASE (aux_addr + 0x0)
83
84 #define AUX_BASE (PER_BASE + AUX_BASE_OFFSET)
85 #define IRQ_PL011 (96 + 57)
86
87 /* Peripheral IRQ OR-ing */
88 #define PACTL_CS_ADDR (PER_BASE + PACTL_CS_OFFSET)
89 extern size_t pactl_cs_base;
90 #define PACTL_CS HWREG32(pactl_cs_base)
91 typedef enum
92 {
93 IRQ_SPI0 = 0x00000000,
94 IRQ_SPI1 = 0x00000002,
95 IRQ_SPI2 = 0x00000004,
96 IRQ_SPI3 = 0x00000008,
97 IRQ_SPI4 = 0x00000010,
98 IRQ_SPI5 = 0x00000020,
99 IRQ_SPI6 = 0x00000040,
100 IRQ_I2C0 = 0x00000100,
101 IRQ_I2C1 = 0x00000200,
102 IRQ_I2C2 = 0x00000400,
103 IRQ_I2C3 = 0x00000800,
104 IRQ_I2C4 = 0x00001000,
105 IRQ_I2C5 = 0x00002000,
106 IRQ_I2C6 = 0x00004000,
107 IRQ_I2C7 = 0x00008000,
108 IRQ_UART5 = 0x00010000,
109 IRQ_UART4 = 0x00020000,
110 IRQ_UART3 = 0x00040000,
111 IRQ_UART2 = 0x00080000,
112 IRQ_UART0 = 0x00100000
113 } PACTL_CS_VAL;
114
115 // 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
116 #define CORE0_TIMER_IRQ_CTRL HWREG32(0xFF800040)
117 #define TIMER_IRQ 30
118 #define NON_SECURE_TIMER_IRQ (1 << 1)
119
120 /* GIC */
121 #define INTC_BASE (0xff800000)
122 #define ARM_GIC_NR_IRQS (512)
123 #define ARM_GIC_MAX_NR (512)
124 #define GIC_V2_BASE (INTC_BASE + 0x00040000)
125 extern size_t gic_base_addr;
126 #define GIC_V2_DISTRIBUTOR_BASE (gic_base_addr + 0x1000)
127 #define GIC_V2_CPU_INTERFACE_BASE (gic_base_addr + 0x2000)
128 #define GIC_V2_HYPERVISOR_BASE (gic_base_addr + 0x4000)
129 #define GIC_V2_VIRTUAL_CPU_BASE (gic_base_addr + 0x6000)
130
131 #define GIC_PL400_DISTRIBUTOR_PPTR GIC_V2_DISTRIBUTOR_BASE
132 #define GIC_PL400_CONTROLLER_PPTR GIC_V2_CPU_INTERFACE_BASE
133
134 #define GIC_IRQ_START 0
135
136 #define GIC_ACK_INTID_MASK 0x000003ff
137
138
139 //watchdog
140 #define WDT_BASE (PER_BASE + 0x00100000)
141 extern size_t wdt_base_addr;
142 #define PM_RSTC HWREG32(wdt_base_addr + 0x1c)
143 #define PM_RSTS HWREG32(wdt_base_addr + 0x20)
144 #define PM_WDOG HWREG32(wdt_base_addr + 0x24)
145
146 #define PM_PASSWORD (0x5A000000)
147 #define PM_WDOG_TIME_SET (0x000fffff)
148 #define PM_RSTS_HADWRH_SET (0x00000040)
149 #define PM_RSTC_WRCFG_FULL_RESET (0x00000020)
150 #define PM_RSTC_WRCFG_CLR (0xffffffcf)
151 #define PM_RSTC_RESET (0x00000102)
152
153 //timer
154 #define ST_BASE_OFFSET (0x003000)
155 #define STIMER_BASE (PER_BASE + ST_BASE_OFFSET)
156 extern size_t stimer_base_addr;
157 #define STIMER_CS __REG32(stimer_base_addr + 0x0000)
158 #define STIMER_CLO __REG32(stimer_base_addr + 0x0004)
159 #define STIMER_CHI __REG32(stimer_base_addr + 0x0008)
160 #define STIMER_C0 __REG32(stimer_base_addr + 0x000C)
161 #define STIMER_C1 __REG32(stimer_base_addr + 0x0010)
162 #define STIMER_C2 __REG32(stimer_base_addr + 0x0014)
163 #define STIMER_C3 __REG32(stimer_base_addr + 0x0018)
164
165 #define DELAY_MICROS(micros) \
166 do{ \
167 rt_uint32_t compare = STIMER_CLO + micros * 25; \
168 while (STIMER_CLO < compare); \
169 } while (0)
170
171 //External Mass Media Controller (SD Card)
172 #define MMC0_BASE_ADDR (PER_BASE+0x300000)
173 extern size_t mmc0_base_addr;
174 #define MMC2_BASE_ADDR (PER_BASE+0x340000)
175 extern size_t mmc2_base_addr;
176
177 //mac
178 #define MAC_REG (void *)(0xfd580000)
179 extern uint8_t * mac_reg_base_addr;
180
181 #define ETH_IRQ (160+29)
182
183 #define SEND_DATA_NO_CACHE (0x08200000)
184 extern uint8_t * eth_send_no_cache;
185
186 #define RECV_DATA_NO_CACHE (0x08400000)
187 extern uint8_t * eth_recv_no_cache;
188
189 /* the basic constants and interfaces needed by gic */
platform_get_gic_dist_base(void)190 rt_inline size_t platform_get_gic_dist_base(void)
191 {
192 return GIC_PL400_DISTRIBUTOR_PPTR;
193 }
194
platform_get_gic_cpu_base(void)195 rt_inline size_t platform_get_gic_cpu_base(void)
196 {
197 return GIC_PL400_CONTROLLER_PPTR;
198 }
199
200 #endif
201