1 /* 2 * Copyright (c) 2006-2025, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018-12-25 zylx first version 9 */ 10 11 #ifndef __DRV_ETH_H__ 12 #define __DRV_ETH_H__ 13 14 #include <rtthread.h> 15 #include <rthw.h> 16 #include <rtdevice.h> 17 #include <board.h> 18 19 /* The PHY basic control register */ 20 #define PHY_BASIC_CONTROL_REG 0x00U 21 #define PHY_RESET_MASK (1<<15) 22 #define PHY_AUTO_NEGOTIATION_MASK (1<<12) 23 24 /* The PHY basic status register */ 25 #define PHY_BASIC_STATUS_REG 0x01U 26 #define PHY_LINKED_STATUS_MASK (1<<2) 27 #define PHY_AUTONEGO_COMPLETE_MASK (1<<5) 28 29 /* The PHY ID one register */ 30 #define PHY_ID1_REG 0x02U 31 /* The PHY ID two register */ 32 #define PHY_ID2_REG 0x03U 33 /* The PHY auto-negotiate advertise register */ 34 #define PHY_AUTONEG_ADVERTISE_REG 0x04U 35 36 37 #ifdef PHY_USING_LAN8720A 38 /* The PHY interrupt source flag register. */ 39 #define PHY_INTERRUPT_FLAG_REG 0x1DU 40 /* The PHY interrupt mask register. */ 41 #define PHY_INTERRUPT_MASK_REG 0x1EU 42 #define PHY_LINK_DOWN_MASK (1<<4) 43 #define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6) 44 45 /* The PHY status register. */ 46 #define PHY_Status_REG 0x1FU 47 #define PHY_10M_MASK (1<<2) 48 #define PHY_100M_MASK (1<<3) 49 #define PHY_FULL_DUPLEX_MASK (1<<4) 50 #define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK) 51 #define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK) 52 #define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK) 53 54 #elif defined(PHY_USING_DM9161CEP) 55 #define PHY_Status_REG 0x11U 56 #define PHY_10M_MASK ((1<<12) || (1<<13)) 57 #define PHY_100M_MASK ((1<<14) || (1<<15)) 58 #define PHY_FULL_DUPLEX_MASK ((1<<15) || (1<<13)) 59 #define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK) 60 #define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK) 61 #define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK) 62 /* The PHY interrupt source flag register. */ 63 #define PHY_INTERRUPT_FLAG_REG 0x15U 64 /* The PHY interrupt mask register. */ 65 #define PHY_INTERRUPT_MASK_REG 0x15U 66 #define PHY_LINK_CHANGE_FLAG (1<<2) 67 #define PHY_LINK_CHANGE_MASK (1<<9) 68 #define PHY_INT_MASK 0 69 70 #elif defined(PHY_USING_DP83848C) 71 #define PHY_Status_REG 0x10U 72 #define PHY_10M_MASK (1<<1) 73 #define PHY_FULL_DUPLEX_MASK (1<<2) 74 #define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK) 75 #define PHY_Status_SPEED_100M(sr) (!PHY_Status_SPEED_10M(sr)) 76 #define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK) 77 /* The PHY interrupt source flag register. */ 78 #define PHY_INTERRUPT_FLAG_REG 0x12U 79 #define PHY_LINK_CHANGE_FLAG (1<<13) 80 /* The PHY interrupt control register. */ 81 #define PHY_INTERRUPT_CTRL_REG 0x11U 82 #define PHY_INTERRUPT_EN ((1<<0)|(1<<1)) 83 /* The PHY interrupt mask register. */ 84 #define PHY_INTERRUPT_MASK_REG 0x12U 85 #define PHY_INT_MASK (1<<5) 86 #endif 87 88 #ifdef PHY_USING_LAN8742A 89 /* The PHY interrupt source flag register. */ 90 #define PHY_INTERRUPT_FLAG_REG 0x1DU 91 /* The PHY interrupt mask register. */ 92 #define PHY_INTERRUPT_MASK_REG 0x1EU 93 #define PHY_LINK_DOWN_MASK (1<<4) 94 #define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6) 95 96 /* The PHY status register. */ 97 #define PHY_Status_REG 0x1FU 98 #define PHY_10M_MASK (1<<2) 99 #define PHY_100M_MASK (1<<3) 100 #define PHY_FULL_DUPLEX_MASK (1<<4) 101 #define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK) 102 #define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK) 103 #define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK) 104 #endif /* PHY_USING_LAN8742A */ 105 106 #define PHY_LINK (1 << 0) 107 #define PHY_100M (1 << 1) 108 #define PING_PORT_COUNT (3) ///< Count of port 109 110 #endif /* __DRV_ETH_H__ */ 111