1 /*
2 * Copyright (c) 2006-2025, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2023-09-04 Rbb666 first version
9 */
10
11 #include "board.h"
12 #include "drv_hwtimer.h"
13
14 //#define DRV_DEBUG
15 #define LOG_TAG "drv.timer"
16 #include <rtdbg.h>
17
18 #ifdef RT_USING_HWTIMER
19
20 static struct ra_hwtimer ra_hwtimer_obj[BSP_TIMERS_NUM] =
21 {
22 #ifdef BSP_USING_TIM0
23 [BSP_TIMER0_INDEX] = TIMER_DRV_INITIALIZER(0),
24 #endif
25 #ifdef BSP_USING_TIM1
26 [BSP_TIMER1_INDEX] = TIMER_DRV_INITIALIZER(1),
27 #endif
28 };
29
30 const rt_uint32_t PLCKD_FREQ_PRESCALER[PLCKD_PRESCALER_MAX_SELECT] =
31 {
32 #if defined(SOC_SERIES_R7FA6M3)
33 PLCKD_PRESCALER_120M,
34 PLCKD_PRESCALER_60M,
35 PLCKD_PRESCALER_30M,
36 PLCKD_PRESCALER_15M,
37 PLCKD_PRESCALER_7_5M,
38 PLCKD_PRESCALER_3_75M,
39 PLCKD_PRESCALER_1_875M,
40 #elif defined(SOC_SERIES_R9A07G0)
41 PLCKD_PRESCALER_400M,
42 PLCKD_PRESCALER_200M,
43 PLCKD_PRESCALER_100M,
44 PLCKD_PRESCALER_50M,
45 PLCKD_PRESCALER_25M,
46 PLCKD_PRESCALER_12_5M,
47 PLCKD_PRESCALER_6_25M,
48 PLCKD_PRESCALER_3_125M,
49 PLCKD_PRESCALER_1_5625M
50 #endif
51 };
52
timer_init(struct rt_hwtimer_device * timer,rt_uint32_t state)53 static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
54 {
55 RT_ASSERT(timer != RT_NULL);
56
57 struct ra_hwtimer *tim;
58 tim = (struct ra_hwtimer *)timer->parent.user_data;
59
60 if (state)
61 {
62 fsp_err_t fsp_err = FSP_SUCCESS;
63
64 fsp_err = R_GPT_Open(tim->g_ctrl, tim->g_cfg);
65
66 if (fsp_err != FSP_SUCCESS)
67 {
68 LOG_E("%s init fail", tim->name);
69 }
70 }
71 }
72
timer_start(rt_hwtimer_t * timer,rt_uint32_t pr,rt_hwtimer_mode_t opmode)73 static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t pr, rt_hwtimer_mode_t opmode)
74 {
75 RT_ASSERT(timer != RT_NULL);
76 RT_ASSERT(opmode != RT_NULL);
77
78 struct ra_hwtimer *tim;
79 tim = (struct ra_hwtimer *)timer->parent.user_data;
80 fsp_err_t err = FSP_SUCCESS;
81
82 /* set timer count */
83 R_GPT_CounterSet(tim->g_ctrl, 0);
84 /* set timer period register */
85 err = R_GPT_PeriodSet(tim->g_ctrl, pr);
86
87 if (err != FSP_SUCCESS)
88 {
89 return -RT_ERROR;
90 }
91
92 /* set timer to one cycle mode */
93 err = R_GPT_Start(tim->g_ctrl);
94
95 return (err == FSP_SUCCESS) ? RT_EOK : -RT_ERROR;
96 }
97
timer_stop(rt_hwtimer_t * timer)98 static void timer_stop(rt_hwtimer_t *timer)
99 {
100 struct ra_hwtimer *tim = RT_NULL;
101
102 RT_ASSERT(timer != RT_NULL);
103 tim = (struct ra_hwtimer *)timer->parent.user_data;
104
105 /* stop timer */
106 R_GPT_Stop(tim->g_ctrl);
107
108 /* set timer count */
109 R_GPT_CounterSet(tim->g_ctrl, 0);
110 }
111
timer_counter_get(rt_hwtimer_t * timer)112 static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
113 {
114 struct ra_hwtimer *tim = RT_NULL;
115
116 RT_ASSERT(timer != RT_NULL);
117
118 tim = (struct ra_hwtimer *)timer->parent.user_data;
119
120 timer_status_t status;
121 if (R_GPT_StatusGet(tim->g_ctrl, &status) != FSP_SUCCESS)
122 return -RT_ERROR;
123
124 return status.counter;
125 }
126
timer_ctrl(rt_hwtimer_t * timer,rt_uint32_t cmd,void * arg)127 static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
128 {
129 rt_err_t result = RT_EOK;
130 struct ra_hwtimer *tim = RT_NULL;
131
132 RT_ASSERT(timer != RT_NULL);
133 RT_ASSERT(arg != RT_NULL);
134
135 tim = (struct ra_hwtimer *)timer->parent.user_data;
136
137 switch (cmd)
138 {
139 case HWTIMER_CTRL_FREQ_SET:
140 {
141 rt_uint8_t index = 0;
142 rt_uint32_t freq = *((rt_uint32_t *)arg);
143
144 for (rt_uint8_t i = 0; i < PLCKD_PRESCALER_MAX_SELECT; i++)
145 {
146 if (freq <= PLCKD_FREQ_PRESCALER[i])
147 {
148 index = i;
149 }
150 }
151 tim->g_ctrl->p_reg->GTCR_b.TPCS = index;
152 }
153 break;
154 default:
155 {
156 result = -RT_ENOSYS;
157 }
158 break;
159 }
160
161 return result;
162 }
163
timer_one_shot_check(void)164 static void timer_one_shot_check(void)
165 {
166 IRQn_Type irq = R_FSP_CurrentIrqGet();
167
168 /* Recover ISR context saved in open. */
169 gpt_instance_ctrl_t *p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
170
171 /* If one-shot mode is selected, stop the timer since period has expired. */
172 if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode)
173 {
174 p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask;
175
176 /* Clear the GPT counter and the overflow flag after the one shot pulse has being generated */
177 p_instance_ctrl->p_reg->GTCNT = 0;
178 p_instance_ctrl->p_reg->GTCCR[0U] = 0;
179 p_instance_ctrl->p_reg->GTCCR[1U] = 0;
180
181 /* Clear pending interrupt to make sure it doesn't fire again if another overflow has already occurred. */
182 R_BSP_IrqClearPending(irq);
183 }
184 }
185
186 #ifdef BSP_USING_TIM0
timer0_callback(timer_callback_args_t * p_args)187 void timer0_callback(timer_callback_args_t *p_args)
188 {
189 /* enter interrupt */
190 rt_interrupt_enter();
191
192 if (TIMER_EVENT_CYCLE_END == p_args->event)
193 {
194 rt_device_hwtimer_isr(&ra_hwtimer_obj[BSP_TIMER0_INDEX].tmr_device);
195
196 timer_one_shot_check();
197 }
198
199 /* leave interrupt */
200 rt_interrupt_leave();
201 }
202 #endif
203
204 #ifdef BSP_USING_TIM1
timer1_callback(timer_callback_args_t * p_args)205 void timer1_callback(timer_callback_args_t *p_args)
206 {
207 /* enter interrupt */
208 rt_interrupt_enter();
209
210 if (TIMER_EVENT_CYCLE_END == p_args->event)
211 {
212 rt_device_hwtimer_isr(&ra_hwtimer_obj[BSP_TIMER1_INDEX].tmr_device);
213
214 timer_one_shot_check();
215 }
216
217 /* leave interrupt */
218 rt_interrupt_leave();
219 }
220 #endif
221
222 static const struct rt_hwtimer_ops _ops =
223 {
224 .init = timer_init,
225 .start = timer_start,
226 .stop = timer_stop,
227 .count_get = timer_counter_get,
228 .control = timer_ctrl,
229 };
230
231 static const struct rt_hwtimer_info _info = TMR_DEV_INFO_CONFIG;
232
rt_hw_hwtimer_init(void)233 static int rt_hw_hwtimer_init(void)
234 {
235 int result = RT_EOK;
236
237 for (int i = 0; i < sizeof(ra_hwtimer_obj) / sizeof(ra_hwtimer_obj[0]); i++)
238 {
239 ra_hwtimer_obj[i].tmr_device.info = &_info;
240 ra_hwtimer_obj[i].tmr_device.ops = &_ops;
241 if (rt_device_hwtimer_register(&ra_hwtimer_obj[i].tmr_device, ra_hwtimer_obj[i].name, &ra_hwtimer_obj[i]) == RT_EOK)
242 {
243 LOG_D("%s register success", ra_hwtimer_obj[i].name);
244 }
245 else
246 {
247 LOG_E("%s register failed", ra_hwtimer_obj[i].name);
248 result = -RT_ERROR;
249 }
250 }
251
252 return result;
253 }
254 INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
255
256 /* This is a hwtimer example */
257 #define HWTIMER_DEV_NAME "timer0" /* device name */
258
timeout_cb(rt_device_t dev,rt_size_t size)259 static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size)
260 {
261 rt_kprintf("this is hwtimer timeout callback fucntion!\n");
262 rt_kprintf("tick is :%d !\n", rt_tick_get());
263
264 return RT_EOK;
265 }
266
hwtimer_sample(void)267 int hwtimer_sample(void)
268 {
269 rt_err_t ret = RT_EOK;
270 rt_hwtimerval_t timeout_s;
271 rt_device_t hw_dev = RT_NULL;
272 rt_hwtimer_mode_t mode;
273 rt_uint32_t freq = 1875000; /* 1Mhz */
274
275 hw_dev = rt_device_find(HWTIMER_DEV_NAME);
276 if (hw_dev == RT_NULL)
277 {
278 rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME);
279 return -RT_ERROR;
280 }
281
282 ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR);
283 if (ret != RT_EOK)
284 {
285 rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME);
286 return ret;
287 }
288
289 rt_device_set_rx_indicate(hw_dev, timeout_cb);
290
291 rt_device_control(hw_dev, HWTIMER_CTRL_FREQ_SET, &freq);
292
293 mode = HWTIMER_MODE_PERIOD;
294 ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode);
295 if (ret != RT_EOK)
296 {
297 rt_kprintf("set mode failed! ret is :%d\n", ret);
298 return ret;
299 }
300
301 /* Example Set the timeout period of the timer */
302 timeout_s.sec = 1; /* secend */
303 timeout_s.usec = 0; /* microsecend */
304 if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s))
305 {
306 rt_kprintf("set timeout value failed\n");
307 return -RT_ERROR;
308 }
309
310 /* read hwtimer value */
311 rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s));
312 rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec);
313
314 return ret;
315 }
316 MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample);
317
318 #endif /* BSP_USING_HWTIMER */
319