1 /*********************************************************************************************************************** 2 * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. 3 * 4 * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products 5 * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are 6 * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use 7 * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property 8 * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas 9 * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION 10 * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT 11 * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES 12 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR 13 * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM 14 * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION 15 * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, 16 * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, 17 * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY 18 * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. 19 **********************************************************************************************************************/ 20 21 /*******************************************************************************************************************//** 22 * @ingroup RENESAS_INTERFACES 23 * @defgroup TRANSFER_API Transfer Interface 24 * 25 * @brief Interface for data transfer functions. 26 * 27 * @section TRANSFER_API_SUMMARY Summary 28 * The transfer interface supports background data transfer (no CPU intervention). 29 * 30 * Implemented by: 31 * - @ref DTC 32 * - @ref DMAC 33 * 34 * @{ 35 **********************************************************************************************************************/ 36 37 #ifndef R_TRANSFER_API_H 38 #define R_TRANSFER_API_H 39 40 /*********************************************************************************************************************** 41 * Includes 42 **********************************************************************************************************************/ 43 44 /* Common error codes and definitions. */ 45 #include "bsp_api.h" 46 47 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 48 FSP_HEADER 49 50 /********************************************************************************************************************** 51 * Macro definitions 52 **********************************************************************************************************************/ 53 54 #define TRANSFER_SETTINGS_MODE_BITS (30U) 55 #define TRANSFER_SETTINGS_SIZE_BITS (28U) 56 #define TRANSFER_SETTINGS_SRC_ADDR_BITS (26U) 57 #define TRANSFER_SETTINGS_CHAIN_MODE_BITS (22U) 58 #define TRANSFER_SETTINGS_IRQ_BITS (21U) 59 #define TRANSFER_SETTINGS_REPEAT_AREA_BITS (20U) 60 #define TRANSFER_SETTINGS_DEST_ADDR_BITS (18U) 61 62 /********************************************************************************************************************** 63 * Typedef definitions 64 **********************************************************************************************************************/ 65 66 /** Transfer control block. Allocate an instance specific control block to pass into the transfer API calls. 67 * @par Implemented as 68 * - dtc_instance_ctrl_t 69 * - dmac_instance_ctrl_t 70 */ 71 typedef void transfer_ctrl_t; 72 73 /** Transfer mode describes what will happen when a transfer request occurs. */ 74 typedef enum e_transfer_mode 75 { 76 /** In normal mode, each transfer request causes a transfer of @ref transfer_size_t from the source pointer to 77 * the destination pointer. The transfer length is decremented and the source and address pointers are 78 * updated according to @ref transfer_addr_mode_t. After the transfer length reaches 0, transfer requests 79 * will not cause any further transfers. */ 80 TRANSFER_MODE_NORMAL = 0, 81 82 /** Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the 83 * repeat area and the transfer length will be reset to their initial values. If DMAC is used, the 84 * transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats 85 * transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is 86 * used, the transfer repeats continuously (no limit to the number of repeat transfers). */ 87 TRANSFER_MODE_REPEAT = 1, 88 89 /** In block mode, each transfer request causes transfer_info_t::length transfers of @ref transfer_size_t. 90 * After each individual transfer, the source and destination pointers are updated according to 91 * @ref transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is 92 * decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any 93 * further transfers. */ 94 TRANSFER_MODE_BLOCK = 2, 95 96 /** In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets 97 * within a block (to split blocks into arrays of their first data, second data, etc.) */ 98 TRANSFER_MODE_REPEAT_BLOCK = 3 99 } transfer_mode_t; 100 101 /** Transfer size specifies the size of each individual transfer. 102 * Total transfer length = transfer_size_t * transfer_length_t 103 */ 104 typedef enum e_transfer_size 105 { 106 TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value 107 TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value 108 TRANSFER_SIZE_4_BYTE = 2 ///< Each transfer transfers a 32-bit value 109 } transfer_size_t; 110 111 /** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */ 112 typedef enum e_transfer_addr_mode 113 { 114 /** Address pointer remains fixed after each transfer. */ 115 TRANSFER_ADDR_MODE_FIXED = 0, 116 117 /** Offset is added to the address pointer after each transfer. */ 118 TRANSFER_ADDR_MODE_OFFSET = 1, 119 120 /** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */ 121 TRANSFER_ADDR_MODE_INCREMENTED = 2, 122 123 /** Address pointer is decremented by associated @ref transfer_size_t after each transfer. */ 124 TRANSFER_ADDR_MODE_DECREMENTED = 3 125 } transfer_addr_mode_t; 126 127 /** Repeat area options (source or destination). In @ref TRANSFER_MODE_REPEAT, the selected pointer returns to its 128 * original value after transfer_info_t::length transfers. In @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT_BLOCK, 129 * the selected pointer returns to its original value after each transfer. */ 130 typedef enum e_transfer_repeat_area 131 { 132 /** Destination area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */ 133 TRANSFER_REPEAT_AREA_DESTINATION = 0, 134 135 /** Source area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */ 136 TRANSFER_REPEAT_AREA_SOURCE = 1 137 } transfer_repeat_area_t; 138 139 /** Chain transfer mode options. 140 * @note Only applies for DTC. */ 141 typedef enum e_transfer_chain_mode 142 { 143 /** Chain mode not used. */ 144 TRANSFER_CHAIN_MODE_DISABLED = 0, 145 146 /** Switch to next transfer after a single transfer from this @ref transfer_info_t. */ 147 TRANSFER_CHAIN_MODE_EACH = 2, 148 149 /** Complete the entire transfer defined in this @ref transfer_info_t before chaining to next transfer. */ 150 TRANSFER_CHAIN_MODE_END = 3 151 } transfer_chain_mode_t; 152 153 /** Interrupt options. */ 154 typedef enum e_transfer_irq 155 { 156 /** Interrupt occurs only after last transfer. If this transfer is chained to a subsequent transfer, 157 * the interrupt will occur only after subsequent chained transfer(s) are complete. 158 * @warning DTC triggers the interrupt of the activation source. Choosing TRANSFER_IRQ_END with DTC will 159 * prevent activation source interrupts until the transfer is complete. */ 160 TRANSFER_IRQ_END = 0, 161 162 /** Interrupt occurs after each transfer. 163 * @note Not available in all HAL drivers. See HAL driver for details. */ 164 TRANSFER_IRQ_EACH = 1 165 } transfer_irq_t; 166 167 /** Driver specific information. */ 168 typedef struct st_transfer_properties 169 { 170 uint32_t block_count_max; ///< Maximum number of blocks 171 uint32_t block_count_remaining; ///< Number of blocks remaining 172 uint32_t transfer_length_max; ///< Maximum number of transfers 173 uint32_t transfer_length_remaining; ///< Number of transfers remaining 174 } transfer_properties_t; 175 176 /** This structure specifies the properties of the transfer. 177 * @warning When using DTC, this structure corresponds to the descriptor block registers required by the DTC. 178 * The following components may be modified by the driver: p_src, p_dest, num_blocks, and length. 179 * @warning When using DTC, do NOT reuse this structure to configure multiple transfers. Each transfer must 180 * have a unique transfer_info_t. 181 * @warning When using DTC, this structure must not be allocated in a temporary location. Any instance of this 182 * structure must remain in scope until the transfer it is used for is closed. 183 * @note When using DTC, consider placing instances of this structure in a protected section of memory. */ 184 typedef struct st_transfer_info 185 { 186 union 187 { 188 struct 189 { 190 uint32_t : 16; 191 uint32_t : 2; 192 193 /** Select what happens to destination pointer after each transfer. */ 194 transfer_addr_mode_t dest_addr_mode : 2; 195 196 /** Select to repeat source or destination area, unused in @ref TRANSFER_MODE_NORMAL. */ 197 transfer_repeat_area_t repeat_area : 1; 198 199 /** Select if interrupts should occur after each individual transfer or after the completion of all planned 200 * transfers. */ 201 transfer_irq_t irq : 1; 202 203 /** Select when the chain transfer ends. */ 204 transfer_chain_mode_t chain_mode : 2; 205 206 uint32_t : 2; 207 208 /** Select what happens to source pointer after each transfer. */ 209 transfer_addr_mode_t src_addr_mode : 2; 210 211 /** Select number of bytes to transfer at once. @see transfer_info_t::length. */ 212 transfer_size_t size : 2; 213 214 /** Select mode from @ref transfer_mode_t. */ 215 transfer_mode_t mode : 2; 216 }; 217 uint32_t transfer_settings_word; 218 }; 219 220 void const * volatile p_src; ///< Source pointer 221 void * volatile p_dest; ///< Destination pointer 222 223 /** Number of blocks to transfer when using @ref TRANSFER_MODE_BLOCK (both DTC an DMAC) or 224 * @ref TRANSFER_MODE_REPEAT (DMAC only) or 225 * @ref TRANSFER_MODE_REPEAT_BLOCK (DMAC only), unused in other modes. */ 226 volatile uint16_t num_blocks; 227 228 /** Length of each transfer. Range limited for @ref TRANSFER_MODE_BLOCK, @ref TRANSFER_MODE_REPEAT, 229 * and @ref TRANSFER_MODE_REPEAT_BLOCK 230 * see HAL driver for details. */ 231 volatile uint16_t length; 232 } transfer_info_t; 233 234 /** Driver configuration set in @ref transfer_api_t::open. All elements except p_extend are required and must be 235 * initialized. */ 236 typedef struct st_transfer_cfg 237 { 238 /** Pointer to transfer configuration options. If using chain transfer (DTC only), this can be a pointer to 239 * an array of chained transfers that will be completed in order. */ 240 transfer_info_t * p_info; 241 242 void const * p_extend; ///< Extension parameter for hardware specific settings. 243 } transfer_cfg_t; 244 245 /** Select whether to start single or repeated transfer with software start. */ 246 typedef enum e_transfer_start_mode 247 { 248 TRANSFER_START_MODE_SINGLE = 0, ///< Software start triggers single transfer. 249 TRANSFER_START_MODE_REPEAT = 1 ///< Software start transfer continues until transfer is complete. 250 } transfer_start_mode_t; 251 252 /** Transfer functions implemented at the HAL layer will follow this API. */ 253 typedef struct st_transfer_api 254 { 255 /** Initial configuration. 256 * @par Implemented as 257 * - @ref R_DTC_Open() 258 * - @ref R_DMAC_Open() 259 * 260 * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. 261 * @param[in] p_cfg Pointer to configuration structure. All elements of this structure 262 * must be set by user. 263 */ 264 fsp_err_t (* open)(transfer_ctrl_t * const p_ctrl, transfer_cfg_t const * const p_cfg); 265 266 /** Reconfigure the transfer. 267 * Enable the transfer if p_info is valid. 268 * @par Implemented as 269 * - @ref R_DTC_Reconfigure() 270 * - @ref R_DMAC_Reconfigure() 271 * 272 * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. 273 * @param[in] p_info Pointer to a new transfer info structure. 274 */ 275 fsp_err_t (* reconfigure)(transfer_ctrl_t * const p_ctrl, transfer_info_t * p_info); 276 277 /** Reset source address pointer, destination address pointer, and/or length, keeping all other settings the same. 278 * Enable the transfer if p_src, p_dest, and length are valid. 279 * @par Implemented as 280 * - @ref R_DTC_Reset() 281 * - @ref R_DMAC_Reset() 282 * 283 * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. 284 * @param[in] p_src Pointer to source. Set to NULL if source pointer should not change. 285 * @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change. 286 * @param[in] num_transfers Transfer length in normal mode or number of blocks in block mode. In DMAC only, 287 * resets number of repeats (initially stored in transfer_info_t::num_blocks) in 288 * repeat mode. Not used in repeat mode for DTC. 289 */ 290 fsp_err_t (* reset)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, 291 uint16_t const num_transfers); 292 293 /** Enable transfer. Transfers occur after the activation source event (or when 294 * @ref transfer_api_t::softwareStart is called if ELC_EVENT_ELC_NONE is chosen as activation source). 295 * @par Implemented as 296 * - @ref R_DTC_Enable() 297 * - @ref R_DMAC_Enable() 298 * 299 * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. 300 */ 301 fsp_err_t (* enable)(transfer_ctrl_t * const p_ctrl); 302 303 /** Disable transfer. Transfers do not occur after the activation source event (or when 304 * @ref transfer_api_t::softwareStart is called if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source). 305 * @note If a transfer is in progress, it will be completed. Subsequent transfer requests do not cause a 306 * transfer. 307 * @par Implemented as 308 * - @ref R_DTC_Disable() 309 * - @ref R_DMAC_Disable() 310 * 311 * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. 312 */ 313 fsp_err_t (* disable)(transfer_ctrl_t * const p_ctrl); 314 315 /** Start transfer in software. 316 * @warning Only works if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source. 317 * @note Not supported for DTC. 318 * @par Implemented as 319 * - @ref R_DMAC_SoftwareStart() 320 * 321 * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. 322 * @param[in] mode Select mode from @ref transfer_start_mode_t. 323 */ 324 fsp_err_t (* softwareStart)(transfer_ctrl_t * const p_ctrl, transfer_start_mode_t mode); 325 326 /** Stop transfer in software. The transfer will stop after completion of the current transfer. 327 * @note Not supported for DTC. 328 * @note Only applies for transfers started with TRANSFER_START_MODE_REPEAT. 329 * @warning Only works if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source. 330 * @par Implemented as 331 * - @ref R_DMAC_SoftwareStop() 332 * 333 * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. 334 */ 335 fsp_err_t (* softwareStop)(transfer_ctrl_t * const p_ctrl); 336 337 /** Provides information about this transfer. 338 * @par Implemented as 339 * - @ref R_DTC_InfoGet() 340 * - @ref R_DMAC_InfoGet() 341 * 342 * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. 343 * @param[out] p_properties Driver specific information. 344 */ 345 fsp_err_t (* infoGet)(transfer_ctrl_t * const p_ctrl, transfer_properties_t * const p_properties); 346 347 /** Releases hardware lock. This allows a transfer to be reconfigured using @ref transfer_api_t::open. 348 * @par Implemented as 349 * - @ref R_DTC_Close() 350 * - @ref R_DMAC_Close() 351 * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. 352 */ 353 fsp_err_t (* close)(transfer_ctrl_t * const p_ctrl); 354 } transfer_api_t; 355 356 /** This structure encompasses everything that is needed to use an instance of this interface. */ 357 typedef struct st_transfer_instance 358 { 359 transfer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance 360 transfer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance 361 transfer_api_t const * p_api; ///< Pointer to the API structure for this instance 362 } transfer_instance_t; 363 364 /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 365 FSP_FOOTER 366 367 #endif 368 369 /*******************************************************************************************************************//** 370 * @} (end defgroup TRANSFER_API) 371 **********************************************************************************************************************/ 372