1 /* 2 * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef R_SCI_UART_H 8 #define R_SCI_UART_H 9 10 /*******************************************************************************************************************//** 11 * @addtogroup SCI_UART 12 * @{ 13 **********************************************************************************************************************/ 14 15 /*********************************************************************************************************************** 16 * Includes 17 **********************************************************************************************************************/ 18 #include "bsp_api.h" 19 #include "r_uart_api.h" 20 #include "r_sci_uart_cfg.h" 21 22 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 23 FSP_HEADER 24 25 /*********************************************************************************************************************** 26 * Macro definitions 27 **********************************************************************************************************************/ 28 29 /********************************************************************************************************************** 30 * Typedef definitions 31 **********************************************************************************************************************/ 32 33 /** Enumeration for SCI clock source */ 34 typedef enum e_sci_clk_src 35 { 36 SCI_UART_CLOCK_INT, /* /< Use internal clock for baud generation */ 37 SCI_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, /* /< Use internal clock for baud generation and output on SCK */ 38 SCI_UART_CLOCK_EXT8X, /* /< Use external clock 8x baud rate */ 39 SCI_UART_CLOCK_EXT16X /* /< Use external clock 16x baud rate */ 40 } sci_clk_src_t; 41 42 /** UART flow control mode definition */ 43 typedef enum e_sci_uart_flow_control 44 { 45 SCI_UART_FLOW_CONTROL_RTS = 0U, /* /< Use SCI pin for RTS */ 46 SCI_UART_FLOW_CONTROL_CTS = 1U, /* /< Use SCI pin for CTS */ 47 SCI_UART_FLOW_CONTROL_CTSRTS = 3U, /* /< Use SCI pin for CTS, external pin for RTS */ 48 SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS = 8U, /* /< Use CTSn_RTSn pin for RTS and CTSn pin for CTS. Available only for some channels on selected MCUs. See hardware manual for channel specific options */ 49 } sci_uart_flow_control_t; 50 51 /** UART instance control block. */ 52 typedef struct st_sci_uart_instance_ctrl 53 { 54 /* Parameters to control UART peripheral device */ 55 uint8_t fifo_depth; /* FIFO depth of the UART channel */ 56 uint8_t rx_transfer_in_progress; /* Set to 1 if a receive transfer is in progress, 0 otherwise */ 57 uint8_t data_bytes : 2; /* 1 byte for 7 or 8 bit data, 2 bytes for 9 bit data */ 58 uint8_t bitrate_modulation : 1; /* 1 if bit rate modulation is enabled, 0 otherwise */ 59 uint32_t open; /* Used to determine if the channel is configured */ 60 61 bsp_io_port_pin_t flow_pin; 62 63 /* Source buffer pointer used to fill hardware FIFO from transmit ISR. */ 64 uint8_t const * p_tx_src; 65 66 /* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */ 67 uint32_t tx_src_bytes; 68 69 /* Destination buffer pointer used for receiving data. */ 70 uint8_t const * p_rx_dest; 71 72 /* Size of destination buffer pointer used for receiving data. */ 73 uint32_t rx_dest_bytes; 74 75 /* Pointer to the configuration block. */ 76 uart_cfg_t const * p_cfg; 77 78 /* Base register for this channel */ 79 R_SCI0_Type * p_reg; 80 81 void (* p_callback)(uart_callback_args_t *); /* Pointer to callback that is called when a uart_event_t occurs. */ 82 uart_callback_args_t * p_callback_memory; /* Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. */ 83 84 /* Pointer to context to be passed into callback function */ 85 void const * p_context; 86 } sci_uart_instance_ctrl_t; 87 88 /** Receive FIFO trigger configuration. */ 89 typedef enum e_sci_uart_rx_fifo_trigger 90 { 91 SCI_UART_RX_FIFO_TRIGGER_1 = 0x1, /* /< Callback after each byte is received without buffering */ 92 SCI_UART_RX_FIFO_TRIGGER_2 = 0x2, /* /< Callback when FIFO having 2 bytes */ 93 SCI_UART_RX_FIFO_TRIGGER_3 = 0x3, /* /< Callback when FIFO having 3 bytes */ 94 SCI_UART_RX_FIFO_TRIGGER_4 = 0x4, /* /< Callback when FIFO having 4 bytes */ 95 SCI_UART_RX_FIFO_TRIGGER_5 = 0x5, /* /< Callback when FIFO having 5 bytes */ 96 SCI_UART_RX_FIFO_TRIGGER_6 = 0x6, /* /< Callback when FIFO having 6 bytes */ 97 SCI_UART_RX_FIFO_TRIGGER_7 = 0x7, /* /< Callback when FIFO having 7 bytes */ 98 SCI_UART_RX_FIFO_TRIGGER_8 = 0x8, /* /< Callback when FIFO having 8 bytes */ 99 SCI_UART_RX_FIFO_TRIGGER_9 = 0x9, /* /< Callback when FIFO having 9 bytes */ 100 SCI_UART_RX_FIFO_TRIGGER_10 = 0xA, /* /< Callback when FIFO having 10 bytes */ 101 SCI_UART_RX_FIFO_TRIGGER_11 = 0xB, /* /< Callback when FIFO having 11 bytes */ 102 SCI_UART_RX_FIFO_TRIGGER_12 = 0xC, /* /< Callback when FIFO having 12 bytes */ 103 SCI_UART_RX_FIFO_TRIGGER_13 = 0xD, /* /< Callback when FIFO having 13 bytes */ 104 SCI_UART_RX_FIFO_TRIGGER_14 = 0xE, /* /< Callback when FIFO having 14 bytes */ 105 SCI_UART_RX_FIFO_TRIGGER_MAX = 0xF, /* /< Callback when FIFO is full or after 15 bit times with no data (fewer interrupts) */ 106 } sci_uart_rx_fifo_trigger_t; 107 108 /** Asynchronous Start Bit Edge Detection configuration. */ 109 typedef enum e_sci_uart_start_bit_t 110 { 111 SCI_UART_START_BIT_LOW_LEVEL = 0x0, /* /< Detect low level on RXDn pin as start bit */ 112 SCI_UART_START_BIT_FALLING_EDGE = 0x1, /* /< Detect falling level on RXDn pin as start bit */ 113 } sci_uart_start_bit_t; 114 115 /** Noise cancellation configuration. */ 116 typedef enum e_sci_uart_noise_cancellation 117 { 118 SCI_UART_NOISE_CANCELLATION_DISABLE = 0x0, /* /< Disable noise cancellation */ 119 SCI_UART_NOISE_CANCELLATION_ENABLE = 0x1, /* /< Enable noise cancellation */ 120 } sci_uart_noise_cancellation_t; 121 122 /** RS-485 Enable/Disable. */ 123 typedef enum e_sci_uart_rs485_enable 124 { 125 SCI_UART_RS485_DISABLE = 0, /* /< RS-485 disabled. */ 126 SCI_UART_RS485_ENABLE = 1, /* /< RS-485 enabled. */ 127 } sci_uart_rs485_enable_t; 128 129 /** The polarity of the RS-485 DE signal. */ 130 typedef enum e_sci_uart_rs485_de_polarity 131 { 132 SCI_UART_RS485_DE_POLARITY_HIGH = 0, /* /< The DE signal is high when a write transfer is in progress. */ 133 SCI_UART_RS485_DE_POLARITY_LOW = 1, /* /< The DE signal is low when a write transfer is in progress. */ 134 } sci_uart_rs485_de_polarity_t; 135 136 /** Register settings to acheive a desired baud rate and modulation duty. */ 137 typedef struct st_baud_setting_t 138 { 139 union 140 { 141 uint8_t semr_baudrate_bits; 142 143 struct 144 { 145 uint8_t : 2; 146 uint8_t brme : 1; /* /< Bit Rate Modulation Enable */ 147 uint8_t abcse : 1; /* /< Asynchronous Mode Extended Base Clock Select 1 */ 148 uint8_t abcs : 1; /* /< Asynchronous Mode Base Clock Select */ 149 uint8_t : 1; 150 uint8_t bgdm : 1; /* /< Baud Rate Generator Double-Speed Mode Select */ 151 uint8_t : 1; 152 } semr_baudrate_bits_b; 153 }; 154 uint8_t cks : 2; /* /< CKS value to get divisor (CKS = N) */ 155 uint8_t brr; /* /< Bit Rate Register setting */ 156 uint8_t mddr; /* /< Modulation Duty Register setting */ 157 } baud_setting_t; 158 159 /** Configuration settings for controlling the DE signal for RS-485. */ 160 typedef struct st_sci_uart_rs485_setting 161 { 162 sci_uart_rs485_enable_t enable; /* /< Enable the DE signal. */ 163 sci_uart_rs485_de_polarity_t polarity; /* /< DE signal polarity. */ 164 bsp_io_port_pin_t de_control_pin; /* /< UART Driver Enable pin. */ 165 } sci_uart_rs485_setting_t; 166 167 /** IrDA Enable/Disable. */ 168 typedef enum e_sci_uart_irda_enable 169 { 170 SCI_UART_IRDA_DISABLED = 0, /* /< IrDA disabled. */ 171 SCI_UART_IRDA_ENABLED = 1, /* /< IrDA enabled. */ 172 } sci_uart_irda_enable_t; 173 174 /** IrDA Polarity Switching. */ 175 typedef enum e_sci_uart_irda_polarity 176 { 177 SCI_UART_IRDA_POLARITY_NORMAL = 0, /* /< IrDA Tx/Rx polarity not inverted. */ 178 SCI_UART_IRDA_POLARITY_INVERTED = 1, /* /< IrDA Tx/Rx polarity inverted. */ 179 } sci_uart_irda_polarity_t; 180 181 /** Configuration settings for IrDA interface. */ 182 typedef struct st_sci_uart_irda_setting 183 { 184 union 185 { 186 uint8_t ircr_bits; 187 188 struct 189 { 190 uint8_t : 2; 191 uint8_t irrxinv : 1; /* /< IRRXD Polarity Switching */ 192 uint8_t irtxinv : 1; /* /< IRTXD Polarity Switching */ 193 uint8_t : 3; 194 uint8_t ire : 1; /* /< Enable IrDA pulse encoding and decoding. */ 195 } ircr_bits_b; 196 }; 197 } sci_uart_irda_setting_t; 198 199 /** UART on SCI device Configuration */ 200 typedef struct st_sci_uart_extended_cfg 201 { 202 sci_clk_src_t clock; /* /< The source clock for the baud-rate generator. If internal optionally output baud rate on SCK */ 203 sci_uart_start_bit_t rx_edge_start; /* /< Start reception on falling edge */ 204 sci_uart_noise_cancellation_t noise_cancel; /* /< Noise cancellation setting */ 205 baud_setting_t * p_baud_setting; /* /< Register settings for a desired baud rate. */ 206 sci_uart_rx_fifo_trigger_t rx_fifo_trigger; /* /< Receive FIFO trigger level, unused if channel has no FIFO or if DTC is used. */ 207 bsp_io_port_pin_t flow_control_pin; /* /< UART Driver Enable pin */ 208 sci_uart_flow_control_t flow_control; /* /< CTS/RTS function of the SSn pin */ 209 sci_uart_rs485_setting_t rs485_setting; /* /< RS-485 settings. */ 210 sci_uart_irda_setting_t irda_setting; /* /< IrDA settings */ 211 } sci_uart_extended_cfg_t; 212 213 /********************************************************************************************************************** 214 * Exported global variables 215 **********************************************************************************************************************/ 216 217 /** @cond INC_HEADER_DEFS_SEC */ 218 /** Filled in Interface API structure for this Instance. */ 219 extern const uart_api_t g_uart_on_sci; 220 221 /** @endcond */ 222 223 fsp_err_t R_SCI_UART_Open(uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg); 224 fsp_err_t R_SCI_UART_Read(uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes); 225 fsp_err_t R_SCI_UART_Write(uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes); 226 fsp_err_t R_SCI_UART_BaudSet(uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting); 227 fsp_err_t R_SCI_UART_InfoGet(uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info); 228 fsp_err_t R_SCI_UART_Close(uart_ctrl_t * const p_api_ctrl); 229 fsp_err_t R_SCI_UART_Abort(uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort); 230 fsp_err_t R_SCI_UART_BaudCalculate(uint32_t baudrate, 231 bool bitrate_modulation, 232 uint32_t baud_rate_error_x_1000, 233 baud_setting_t * const p_baud_setting); 234 fsp_err_t R_SCI_UART_CallbackSet(uart_ctrl_t * const p_api_ctrl, 235 void ( * p_callback)(uart_callback_args_t *), 236 void const * const p_context, 237 uart_callback_args_t * const p_callback_memory); 238 fsp_err_t R_SCI_UART_ReadStop(uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes); 239 240 /*******************************************************************************************************************//** 241 * @} (end addtogroup SCI_UART) 242 **********************************************************************************************************************/ 243 244 /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 245 FSP_FOOTER 246 247 #endif 248 249