1 /*********************************************************************************************************************** 2 * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. 3 * 4 * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products 5 * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are 6 * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use 7 * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property 8 * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas 9 * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION 10 * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT 11 * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES 12 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR 13 * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM 14 * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION 15 * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, 16 * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, 17 * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY 18 * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. 19 **********************************************************************************************************************/ 20 /*******************************************************************************************************************//** 21 * @ingroup RENESAS_INTERFACES 22 * @defgroup IOPORT_API I/O Port Interface 23 * @brief Interface for accessing I/O ports and configuring I/O functionality. 24 * 25 * @section IOPORT_API_SUMMARY Summary 26 * The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level. 27 * Port and pin direction can be changed. 28 * 29 * IOPORT Interface description: @ref IOPORT 30 * 31 * @{ 32 **********************************************************************************************************************/ 33 34 #ifndef R_IOPORT_API_H 35 #define R_IOPORT_API_H 36 37 /*********************************************************************************************************************** 38 * Includes 39 **********************************************************************************************************************/ 40 41 /* Common error codes and definitions. */ 42 #include "bsp_api.h" 43 44 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 45 FSP_HEADER 46 47 /********************************************************************************************************************** 48 * Macro definitions 49 **********************************************************************************************************************/ 50 51 /* Private definition to set enumeration values. */ 52 #define IOPORT_PRV_PFS_PSEL_OFFSET (24) 53 54 /********************************************************************************************************************** 55 * Typedef definitions 56 **********************************************************************************************************************/ 57 58 /** IO port type used with ports */ 59 typedef uint16_t ioport_size_t; ///< IO port size on this device 60 61 /** Superset of all peripheral functions. */ 62 typedef enum e_ioport_peripheral 63 { 64 /** Pin will functions as an IO pin */ 65 IOPORT_PERIPHERAL_IO = 0x00, 66 67 /** Pin will function as a DEBUG pin */ 68 IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET), 69 70 /** Pin will function as an AGT peripheral pin */ 71 IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), 72 73 /** Pin will function as an AGT peripheral pin */ 74 IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), 75 76 /** Pin will function as an AGT peripheral pin */ 77 IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), 78 79 /** Pin will function as a GPT peripheral pin */ 80 IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET), 81 82 /** Pin will function as a GPT peripheral pin */ 83 IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET), 84 85 /** Pin will function as an SCI peripheral pin */ 86 IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET), 87 88 /** Pin will function as an SCI peripheral pin */ 89 IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET), 90 91 /** Pin will function as a SPI peripheral pin */ 92 IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET), 93 94 /** Pin will function as a IIC peripheral pin */ 95 IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET), 96 97 /** Pin will function as a KEY peripheral pin */ 98 IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET), 99 100 /** Pin will function as a clock/comparator/RTC peripheral pin */ 101 IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET), 102 103 /** Pin will function as a CAC/ADC peripheral pin */ 104 IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET), 105 106 /** Pin will function as a BUS peripheral pin */ 107 IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET), 108 109 /** Pin will function as a CTSU peripheral pin */ 110 IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), 111 112 /** Pin will function as a CMPHS peripheral pin */ 113 IOPORT_PERIPHERAL_ACMPHS = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), 114 115 /** Pin will function as a segment LCD peripheral pin */ 116 IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), 117 118 /** Pin will function as an SCI peripheral DEn pin */ 119 IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), 120 121 /** Pin will function as a DALI peripheral pin */ 122 IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), 123 124 /** Pin will function as an SCI DEn peripheral pin */ 125 IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), 126 127 /** Pin will function as a CEU peripheral pin */ 128 IOPORT_PERIPHERAL_CEU = (0x0FUL << IOPORT_PRV_PFS_PSEL_OFFSET), 129 130 /** Pin will function as a CAN peripheral pin */ 131 IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET), 132 133 /** Pin will function as a QSPI peripheral pin */ 134 IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET), 135 136 /** Pin will function as an SSI peripheral pin */ 137 IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET), 138 139 /** Pin will function as a USB full speed peripheral pin */ 140 IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET), 141 142 /** Pin will function as a USB high speed peripheral pin */ 143 IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), 144 145 /** Pin will function as a GPT peripheral pin */ 146 IOPORT_PERIPHERAL_GPT2 = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), 147 148 /** Pin will function as an SD/MMC peripheral pin */ 149 IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), 150 151 /** Pin will function as a GPT peripheral pin */ 152 IOPORT_PERIPHERAL_GPT3 = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), 153 154 /** Pin will function as an Ethernet MMI peripheral pin */ 155 IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), 156 157 /** Pin will function as a GPT peripheral pin */ 158 IOPORT_PERIPHERAL_GPT4 = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), 159 160 /** Pin will function as an Ethernet RMMI peripheral pin */ 161 IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET), 162 163 /** Pin will function as a PDC peripheral pin */ 164 IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), 165 166 /** Pin will function as a graphics LCD peripheral pin */ 167 IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), 168 169 /** Pin will function as a CAC peripheral pin */ 170 IOPORT_PERIPHERAL_CAC = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), 171 172 /** Pin will function as a debug trace peripheral pin */ 173 IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET), 174 175 /** Pin will function as a OSPI peripheral pin */ 176 IOPORT_PERIPHERAL_OSPI = (0x1CUL << IOPORT_PRV_PFS_PSEL_OFFSET), 177 178 /** Pin will function as a CEC peripheral pin */ 179 IOPORT_PERIPHERAL_CEC = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), 180 181 /** Pin will function as a PGAOUT peripheral pin */ 182 IOPORT_PERIPHERAL_PGAOUT0 = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), 183 184 /** Pin will function as a PGAOUT peripheral pin */ 185 IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), 186 187 /** Pin will function as a MIPI peripheral pin */ 188 IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET), 189 190 /** Pin will function as a ULPT peripheral pin */ 191 IOPORT_PERIPHERAL_ULPT = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), 192 } ioport_peripheral_t; 193 194 /** Options to configure pin functions */ 195 typedef enum e_ioport_cfg_options 196 { 197 IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000000, ///< Sets the pin direction to input (default) 198 IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000004, ///< Sets the pin direction to output 199 IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000, ///< Sets the pin level to low 200 IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001, ///< Sets the pin level to high 201 IOPORT_CFG_PULLUP_ENABLE = 0x00000010, ///< Enables the pin's internal pull-up 202 IOPORT_CFG_PIM_TTL = 0x00000020, ///< Enables the pin's input mode 203 IOPORT_CFG_NMOS_ENABLE = 0x00000040, ///< Enables the pin's NMOS open-drain output 204 IOPORT_CFG_PMOS_ENABLE = 0x00000080, ///< Enables the pin's PMOS open-drain ouput 205 IOPORT_CFG_DRIVE_MID = 0x00000400, ///< Sets pin drive output to medium 206 IOPORT_CFG_DRIVE_HS_HIGH = 0x00000800, ///< Sets pin drive output to high along with supporting high speed 207 IOPORT_CFG_DRIVE_MID_IIC = 0x00000C00, ///< Sets pin to drive output needed for IIC on a 20mA port 208 IOPORT_CFG_DRIVE_HIGH = 0x00000C00, ///< Sets pin drive output to high 209 IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, ///< Sets pin event trigger to rising edge 210 IOPORT_CFG_EVENT_FALLING_EDGE = 0x00002000, ///< Sets pin event trigger to falling edge 211 IOPORT_CFG_EVENT_BOTH_EDGES = 0x00003000, ///< Sets pin event trigger to both edges 212 IOPORT_CFG_IRQ_ENABLE = 0x00004000, ///< Sets pin as an IRQ pin 213 IOPORT_CFG_ANALOG_ENABLE = 0x00008000, ///< Enables pin to operate as an analog pin 214 IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< Enables pin to operate as a peripheral pin 215 } ioport_cfg_options_t; 216 217 /* PFS writing enable/disable. */ 218 typedef enum e_ioport_pwpr 219 { 220 IOPORT_PFS_WRITE_DISABLE = 0, ///< Disable PFS write access 221 IOPORT_PFS_WRITE_ENABLE = 1 ///< Enable PFS write access 222 } ioport_pwpr_t; 223 224 /** Pin identifier and pin PFS pin configuration value */ 225 typedef struct st_ioport_pin_cfg 226 { 227 uint32_t pin_cfg; ///< Pin PFS configuration - Use ioport_cfg_options_t parameters to configure 228 bsp_io_port_pin_t pin; ///< Pin identifier 229 } ioport_pin_cfg_t; 230 231 /** Multiple pin configuration data for loading into PFS registers by R_IOPORT_Init() */ 232 typedef struct st_ioport_cfg 233 { 234 uint16_t number_of_pins; ///< Number of pins for which there is configuration data 235 ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data 236 } ioport_cfg_t; 237 238 /** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls. 239 * @par Implemented as 240 * - ioport_instance_ctrl_t 241 */ 242 typedef void ioport_ctrl_t; 243 244 /** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */ 245 typedef struct st_ioport_api 246 { 247 /** Initialize internal driver data and initial pin configurations. Called during startup. Do 248 * not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of 249 * multiple pins. 250 * @par Implemented as 251 * - @ref R_IOPORT_Open() 252 * @param[in] p_cfg Pointer to pin configuration data array. 253 */ 254 fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); 255 256 /** Close the API. 257 * @par Implemented as 258 * - @ref R_IOPORT_Close() 259 * 260 * @param[in] p_ctrl Pointer to control structure. 261 **/ 262 fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl); 263 264 /** Configure multiple pins. 265 * @par Implemented as 266 * - @ref R_IOPORT_PinsCfg() 267 * @param[in] p_cfg Pointer to pin configuration data array. 268 */ 269 fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); 270 271 /** Configure settings for an individual pin. 272 * @par Implemented as 273 * - @ref R_IOPORT_PinCfg() 274 * @param[in] pin Pin to be read. 275 * @param[in] cfg Configuration options for the pin. 276 */ 277 fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); 278 279 /** Read the event input data of the specified pin and return the level. 280 * @par Implemented as 281 * - @ref R_IOPORT_PinEventInputRead() 282 * @param[in] pin Pin to be read. 283 * @param[in] p_pin_event Pointer to return the event data. 284 */ 285 fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); 286 287 /** Write pin event data. 288 * @par Implemented as 289 * - @ref R_IOPORT_PinEventOutputWrite() 290 * @param[in] pin Pin event data is to be written to. 291 * @param[in] pin_value Level to be written to pin output event. 292 */ 293 fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); 294 295 /** Read level of a pin. 296 * @par Implemented as 297 * - @ref R_IOPORT_PinRead() 298 * @param[in] pin Pin to be read. 299 * @param[in] p_pin_value Pointer to return the pin level. 300 */ 301 fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); 302 303 /** Write specified level to a pin. 304 * @par Implemented as 305 * - @ref R_IOPORT_PinWrite() 306 * @param[in] pin Pin to be written to. 307 * @param[in] level State to be written to the pin. 308 */ 309 fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); 310 311 /** Set the direction of one or more pins on a port. 312 * @par Implemented as 313 * - @ref R_IOPORT_PortDirectionSet() 314 * @param[in] port Port being configured. 315 * @param[in] direction_values Value controlling direction of pins on port (1 - output, 0 - input). 316 * @param[in] mask Mask controlling which pins on the port are to be configured. 317 */ 318 fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values, 319 ioport_size_t mask); 320 321 /** Read captured event data for a port. 322 * @par Implemented as 323 * - @ref R_IOPORT_PortEventInputRead() 324 * @param[in] port Port to be read. 325 * @param[in] p_event_data Pointer to return the event data. 326 */ 327 fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data); 328 329 /** Write event output data for a port. 330 * @par Implemented as 331 * - @ref R_IOPORT_PortEventOutputWrite() 332 * @param[in] port Port event data will be written to. 333 * @param[in] event_data Data to be written as event data to specified port. 334 * @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data. 335 * being written to port. 336 */ 337 fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data, 338 ioport_size_t mask_value); 339 340 /** Read states of pins on the specified port. 341 * @par Implemented as 342 * - @ref R_IOPORT_PortRead() 343 * @param[in] port Port to be read. 344 * @param[in] p_port_value Pointer to return the port value. 345 */ 346 fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); 347 348 /** Write to multiple pins on a port. 349 * @par Implemented as 350 * - @ref R_IOPORT_PortWrite() 351 * @param[in] port Port to be written to. 352 * @param[in] value Value to be written to the port. 353 * @param[in] mask Mask controlling which pins on the port are written to. 354 */ 355 fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); 356 } ioport_api_t; 357 358 /** This structure encompasses everything that is needed to use an instance of this interface. */ 359 typedef struct st_ioport_instance 360 { 361 ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance 362 ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance 363 ioport_api_t const * p_api; ///< Pointer to the API structure for this instance 364 } ioport_instance_t; 365 366 /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 367 FSP_FOOTER 368 369 #endif 370 371 /*******************************************************************************************************************//** 372 * @} (end defgroup IOPORT_API) 373 **********************************************************************************************************************/ 374