1 /*********************************************************************************************************************** 2 * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. 3 * 4 * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products 5 * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are 6 * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use 7 * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property 8 * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas 9 * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION 10 * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT 11 * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES 12 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR 13 * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM 14 * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION 15 * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, 16 * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, 17 * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY 18 * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. 19 **********************************************************************************************************************/ 20 21 /*******************************************************************************************************************//** 22 * @ingroup RENESAS_INTERFACES 23 * @defgroup TRANSFER_API Transfer Interface 24 * 25 * @brief Interface for data transfer functions. 26 * 27 * @section TRANSFER_API_SUMMARY Summary 28 * The transfer interface supports background data transfer (no CPU intervention). 29 * 30 * 31 * @{ 32 **********************************************************************************************************************/ 33 34 #ifndef R_TRANSFER_API_H 35 #define R_TRANSFER_API_H 36 37 /*********************************************************************************************************************** 38 * Includes 39 **********************************************************************************************************************/ 40 41 /* Common error codes and definitions. */ 42 #include "bsp_api.h" 43 44 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 45 FSP_HEADER 46 47 /********************************************************************************************************************** 48 * Macro definitions 49 **********************************************************************************************************************/ 50 51 #define TRANSFER_SETTINGS_MODE_BITS (30U) 52 #define TRANSFER_SETTINGS_SIZE_BITS (28U) 53 #define TRANSFER_SETTINGS_SRC_ADDR_BITS (26U) 54 #define TRANSFER_SETTINGS_CHAIN_MODE_BITS (22U) 55 #define TRANSFER_SETTINGS_IRQ_BITS (21U) 56 #define TRANSFER_SETTINGS_REPEAT_AREA_BITS (20U) 57 #define TRANSFER_SETTINGS_DEST_ADDR_BITS (18U) 58 59 /********************************************************************************************************************** 60 * Typedef definitions 61 **********************************************************************************************************************/ 62 63 /** Transfer control block. Allocate an instance specific control block to pass into the transfer API calls. 64 */ 65 typedef void transfer_ctrl_t; 66 67 #ifndef BSP_OVERRIDE_TRANSFER_MODE_T 68 69 /** Transfer mode describes what will happen when a transfer request occurs. */ 70 typedef enum e_transfer_mode 71 { 72 /** In normal mode, each transfer request causes a transfer of @ref transfer_size_t from the source pointer to 73 * the destination pointer. The transfer length is decremented and the source and address pointers are 74 * updated according to @ref transfer_addr_mode_t. After the transfer length reaches 0, transfer requests 75 * will not cause any further transfers. */ 76 TRANSFER_MODE_NORMAL = 0, 77 78 /** Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the 79 * repeat area and the transfer length will be reset to their initial values. If DMAC is used, the 80 * transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats 81 * transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is 82 * used, the transfer repeats continuously (no limit to the number of repeat transfers). */ 83 TRANSFER_MODE_REPEAT = 1, 84 85 /** In block mode, each transfer request causes transfer_info_t::length transfers of @ref transfer_size_t. 86 * After each individual transfer, the source and destination pointers are updated according to 87 * @ref transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is 88 * decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any 89 * further transfers. */ 90 TRANSFER_MODE_BLOCK = 2, 91 92 /** In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets 93 * within a block (to split blocks into arrays of their first data, second data, etc.) */ 94 TRANSFER_MODE_REPEAT_BLOCK = 3 95 } transfer_mode_t; 96 97 #endif 98 99 #ifndef BSP_OVERRIDE_TRANSFER_SIZE_T 100 101 /** Transfer size specifies the size of each individual transfer. 102 * Total transfer length = transfer_size_t * transfer_length_t 103 */ 104 typedef enum e_transfer_size 105 { 106 TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value 107 TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value 108 TRANSFER_SIZE_4_BYTE = 2 ///< Each transfer transfers a 32-bit value 109 } transfer_size_t; 110 111 #endif 112 113 #ifndef BSP_OVERRIDE_TRANSFER_ADDR_MODE_T 114 115 /** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */ 116 typedef enum e_transfer_addr_mode 117 { 118 /** Address pointer remains fixed after each transfer. */ 119 TRANSFER_ADDR_MODE_FIXED = 0, 120 121 /** Offset is added to the address pointer after each transfer. */ 122 TRANSFER_ADDR_MODE_OFFSET = 1, 123 124 /** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */ 125 TRANSFER_ADDR_MODE_INCREMENTED = 2, 126 127 /** Address pointer is decremented by associated @ref transfer_size_t after each transfer. */ 128 TRANSFER_ADDR_MODE_DECREMENTED = 3 129 } transfer_addr_mode_t; 130 131 #endif 132 133 #ifndef BSP_OVERRIDE_TRANSFER_REPEAT_AREA_T 134 135 /** Repeat area options (source or destination). In @ref TRANSFER_MODE_REPEAT, the selected pointer returns to its 136 * original value after transfer_info_t::length transfers. In @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT_BLOCK, 137 * the selected pointer returns to its original value after each transfer. */ 138 typedef enum e_transfer_repeat_area 139 { 140 /** Destination area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */ 141 TRANSFER_REPEAT_AREA_DESTINATION = 0, 142 143 /** Source area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */ 144 TRANSFER_REPEAT_AREA_SOURCE = 1 145 } transfer_repeat_area_t; 146 147 #endif 148 149 #ifndef BSP_OVERRIDE_TRANSFER_CHAIN_MODE_T 150 151 /** Chain transfer mode options. 152 * @note Only applies for DTC. */ 153 typedef enum e_transfer_chain_mode 154 { 155 /** Chain mode not used. */ 156 TRANSFER_CHAIN_MODE_DISABLED = 0, 157 158 /** Switch to next transfer after a single transfer from this @ref transfer_info_t. */ 159 TRANSFER_CHAIN_MODE_EACH = 2, 160 161 /** Complete the entire transfer defined in this @ref transfer_info_t before chaining to next transfer. */ 162 TRANSFER_CHAIN_MODE_END = 3 163 } transfer_chain_mode_t; 164 165 #endif 166 167 #ifndef BSP_OVERRIDE_TRANSFER_IRQ_T 168 169 /** Interrupt options. */ 170 typedef enum e_transfer_irq 171 { 172 /** Interrupt occurs only after last transfer. If this transfer is chained to a subsequent transfer, 173 * the interrupt will occur only after subsequent chained transfer(s) are complete. 174 * @warning DTC triggers the interrupt of the activation source. Choosing TRANSFER_IRQ_END with DTC will 175 * prevent activation source interrupts until the transfer is complete. */ 176 TRANSFER_IRQ_END = 0, 177 178 /** Interrupt occurs after each transfer. 179 * @note Not available in all HAL drivers. See HAL driver for details. */ 180 TRANSFER_IRQ_EACH = 1 181 } transfer_irq_t; 182 183 #endif 184 185 /** Driver specific information. */ 186 typedef struct st_transfer_properties 187 { 188 uint32_t block_count_max; ///< Maximum number of blocks 189 uint32_t block_count_remaining; ///< Number of blocks remaining 190 uint32_t transfer_length_max; ///< Maximum number of transfers 191 uint32_t transfer_length_remaining; ///< Number of transfers remaining 192 } transfer_properties_t; 193 194 #ifndef BSP_OVERRIDE_TRANSFER_INFO_T 195 196 /** This structure specifies the properties of the transfer. 197 * @warning When using DTC, this structure corresponds to the descriptor block registers required by the DTC. 198 * The following components may be modified by the driver: p_src, p_dest, num_blocks, and length. 199 * @warning When using DTC, do NOT reuse this structure to configure multiple transfers. Each transfer must 200 * have a unique transfer_info_t. 201 * @warning When using DTC, this structure must not be allocated in a temporary location. Any instance of this 202 * structure must remain in scope until the transfer it is used for is closed. 203 * @note When using DTC, consider placing instances of this structure in a protected section of memory. */ 204 typedef struct st_transfer_info 205 { 206 union 207 { 208 struct 209 { 210 uint32_t : 16; 211 uint32_t : 2; 212 213 /** Select what happens to destination pointer after each transfer. */ 214 transfer_addr_mode_t dest_addr_mode : 2; 215 216 /** Select to repeat source or destination area, unused in @ref TRANSFER_MODE_NORMAL. */ 217 transfer_repeat_area_t repeat_area : 1; 218 219 /** Select if interrupts should occur after each individual transfer or after the completion of all planned 220 * transfers. */ 221 transfer_irq_t irq : 1; 222 223 /** Select when the chain transfer ends. */ 224 transfer_chain_mode_t chain_mode : 2; 225 226 uint32_t : 2; 227 228 /** Select what happens to source pointer after each transfer. */ 229 transfer_addr_mode_t src_addr_mode : 2; 230 231 /** Select number of bytes to transfer at once. @see transfer_info_t::length. */ 232 transfer_size_t size : 2; 233 234 /** Select mode from @ref transfer_mode_t. */ 235 transfer_mode_t mode : 2; 236 } transfer_settings_word_b; 237 238 uint32_t transfer_settings_word; 239 }; 240 241 void const * volatile p_src; ///< Source pointer 242 void * volatile p_dest; ///< Destination pointer 243 244 /** Number of blocks to transfer when using @ref TRANSFER_MODE_BLOCK (both DTC an DMAC) or 245 * @ref TRANSFER_MODE_REPEAT (DMAC only) or 246 * @ref TRANSFER_MODE_REPEAT_BLOCK (DMAC only), unused in other modes. */ 247 volatile uint16_t num_blocks; 248 249 /** Length of each transfer. Range limited for @ref TRANSFER_MODE_BLOCK, @ref TRANSFER_MODE_REPEAT, 250 * and @ref TRANSFER_MODE_REPEAT_BLOCK 251 * see HAL driver for details. */ 252 volatile uint16_t length; 253 } transfer_info_t; 254 255 #endif 256 257 /** Driver configuration set in @ref transfer_api_t::open. All elements except p_extend are required and must be 258 * initialized. */ 259 typedef struct st_transfer_cfg 260 { 261 /** Pointer to transfer configuration options. If using chain transfer (DTC only), this can be a pointer to 262 * an array of chained transfers that will be completed in order. */ 263 transfer_info_t * p_info; 264 265 void const * p_extend; ///< Extension parameter for hardware specific settings. 266 } transfer_cfg_t; 267 268 /** Select whether to start single or repeated transfer with software start. */ 269 typedef enum e_transfer_start_mode 270 { 271 TRANSFER_START_MODE_SINGLE = 0, ///< Software start triggers single transfer. 272 TRANSFER_START_MODE_REPEAT = 1 ///< Software start transfer continues until transfer is complete. 273 } transfer_start_mode_t; 274 275 /** Transfer functions implemented at the HAL layer will follow this API. */ 276 typedef struct st_transfer_api 277 { 278 /** Initial configuration. 279 * 280 * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. 281 * @param[in] p_cfg Pointer to configuration structure. All elements of this structure 282 * must be set by user. 283 */ 284 fsp_err_t (* open)(transfer_ctrl_t * const p_ctrl, transfer_cfg_t const * const p_cfg); 285 286 /** Reconfigure the transfer. 287 * Enable the transfer if p_info is valid. 288 * 289 * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. 290 * @param[in] p_info Pointer to a new transfer info structure. 291 */ 292 fsp_err_t (* reconfigure)(transfer_ctrl_t * const p_ctrl, transfer_info_t * p_info); 293 294 /** Reset source address pointer, destination address pointer, and/or length, keeping all other settings the same. 295 * Enable the transfer if p_src, p_dest, and length are valid. 296 * 297 * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. 298 * @param[in] p_src Pointer to source. Set to NULL if source pointer should not change. 299 * @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change. 300 * @param[in] num_transfers Transfer length in normal mode or number of blocks in block mode. In DMAC only, 301 * resets number of repeats (initially stored in transfer_info_t::num_blocks) in 302 * repeat mode. Not used in repeat mode for DTC. 303 */ 304 fsp_err_t (* reset)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, 305 uint16_t const num_transfers); 306 307 /** Enable transfer. Transfers occur after the activation source event (or when 308 * @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as activation source). 309 * 310 * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. 311 */ 312 fsp_err_t (* enable)(transfer_ctrl_t * const p_ctrl); 313 314 /** Disable transfer. Transfers do not occur after the activation source event (or when 315 * @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as the DMAC activation source). 316 * @note If a transfer is in progress, it will be completed. Subsequent transfer requests do not cause a 317 * transfer. 318 * 319 * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. 320 */ 321 fsp_err_t (* disable)(transfer_ctrl_t * const p_ctrl); 322 323 /** Start transfer in software. 324 * @warning Only works if no peripheral event is chosen as the DMAC activation source. 325 * @note Not supported for DTC. 326 * 327 * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. 328 * @param[in] mode Select mode from @ref transfer_start_mode_t. 329 */ 330 fsp_err_t (* softwareStart)(transfer_ctrl_t * const p_ctrl, transfer_start_mode_t mode); 331 332 /** Stop transfer in software. The transfer will stop after completion of the current transfer. 333 * @note Not supported for DTC. 334 * @note Only applies for transfers started with TRANSFER_START_MODE_REPEAT. 335 * @warning Only works if no peripheral event is chosen as the DMAC activation source. 336 * 337 * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. 338 */ 339 fsp_err_t (* softwareStop)(transfer_ctrl_t * const p_ctrl); 340 341 /** Provides information about this transfer. 342 * 343 * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. 344 * @param[out] p_properties Driver specific information. 345 */ 346 fsp_err_t (* infoGet)(transfer_ctrl_t * const p_ctrl, transfer_properties_t * const p_properties); 347 348 /** Releases hardware lock. This allows a transfer to be reconfigured using @ref transfer_api_t::open. 349 * 350 * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. 351 */ 352 fsp_err_t (* close)(transfer_ctrl_t * const p_ctrl); 353 354 /** To update next transfer information without interruption during transfer. 355 * Allow further transfer continuation. 356 * 357 * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. 358 * @param[in] p_src Pointer to source. Set to NULL if source pointer should not change. 359 * @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change. 360 * @param[in] num_transfers Transfer length in normal mode or block mode. 361 */ 362 fsp_err_t (* reload)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, 363 uint32_t const num_transfers); 364 } transfer_api_t; 365 366 /** This structure encompasses everything that is needed to use an instance of this interface. */ 367 typedef struct st_transfer_instance 368 { 369 transfer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance 370 transfer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance 371 transfer_api_t const * p_api; ///< Pointer to the API structure for this instance 372 } transfer_instance_t; 373 374 /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 375 FSP_FOOTER 376 377 #endif 378 379 /*******************************************************************************************************************//** 380 * @} (end defgroup TRANSFER_API) 381 **********************************************************************************************************************/ 382