1 /*********************************************************************************************************************** 2 * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. 3 * 4 * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products 5 * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are 6 * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use 7 * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property 8 * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas 9 * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION 10 * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT 11 * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES 12 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR 13 * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM 14 * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION 15 * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, 16 * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, 17 * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY 18 * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. 19 **********************************************************************************************************************/ 20 21 #ifndef FSP_FEATURES_H 22 #define FSP_FEATURES_H 23 24 /*********************************************************************************************************************** 25 * Includes <System Includes> , "Project Includes" 26 **********************************************************************************************************************/ 27 28 /* C99 includes. */ 29 #include <stdint.h> 30 #include <stddef.h> 31 #include <stdbool.h> 32 #include <assert.h> 33 34 /* Different compiler support. */ 35 #include "fsp_common_api.h" 36 #include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h" 37 38 /*********************************************************************************************************************** 39 * Macro definitions 40 **********************************************************************************************************************/ 41 42 /*******************************************************************************************************************//** 43 * @addtogroup BSP_MCU 44 * @{ 45 **********************************************************************************************************************/ 46 47 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 48 FSP_HEADER 49 50 /*********************************************************************************************************************** 51 * Typedef definitions 52 **********************************************************************************************************************/ 53 54 /** Available modules. */ 55 typedef enum e_fsp_ip 56 { 57 FSP_IP_CFLASH = 0, ///< Code Flash 58 FSP_IP_DFLASH = 1, ///< Data Flash 59 FSP_IP_RAM = 2, ///< RAM 60 FSP_IP_LVD = 3, ///< Low Voltage Detection 61 FSP_IP_CGC = 3, ///< Clock Generation Circuit 62 FSP_IP_LPM = 3, ///< Low Power Modes 63 FSP_IP_FCU = 4, ///< Flash Control Unit 64 FSP_IP_ICU = 6, ///< Interrupt Control Unit 65 FSP_IP_DMAC = 7, ///< DMA Controller 66 FSP_IP_DTC = 8, ///< Data Transfer Controller 67 FSP_IP_IOPORT = 9, ///< I/O Ports 68 FSP_IP_PFS = 10, ///< Pin Function Select 69 FSP_IP_ELC = 11, ///< Event Link Controller 70 FSP_IP_MPU = 13, ///< Memory Protection Unit 71 FSP_IP_MSTP = 14, ///< Module Stop 72 FSP_IP_MMF = 15, ///< Memory Mirror Function 73 FSP_IP_KEY = 16, ///< Key Interrupt Function 74 FSP_IP_CAC = 17, ///< Clock Frequency Accuracy Measurement Circuit 75 FSP_IP_DOC = 18, ///< Data Operation Circuit 76 FSP_IP_CRC = 19, ///< Cyclic Redundancy Check Calculator 77 FSP_IP_SCI = 20, ///< Serial Communications Interface 78 FSP_IP_IIC = 21, ///< I2C Bus Interface 79 FSP_IP_SPI = 22, ///< Serial Peripheral Interface 80 FSP_IP_CTSU = 23, ///< Capacitive Touch Sensing Unit 81 FSP_IP_SCE = 24, ///< Secure Cryptographic Engine 82 FSP_IP_SLCDC = 25, ///< Segment LCD Controller 83 FSP_IP_AES = 26, ///< Advanced Encryption Standard 84 FSP_IP_TRNG = 27, ///< True Random Number Generator 85 FSP_IP_FCACHE = 30, ///< Flash Cache 86 FSP_IP_SRAM = 31, ///< SRAM 87 FSP_IP_ADC = 32, ///< A/D Converter 88 FSP_IP_DAC = 33, ///< 12-Bit D/A Converter 89 FSP_IP_TSN = 34, ///< Temperature Sensor 90 FSP_IP_DAAD = 35, ///< D/A A/D Synchronous Unit 91 FSP_IP_ACMPHS = 36, ///< High Speed Analog Comparator 92 FSP_IP_ACMPLP = 37, ///< Low Power Analog Comparator 93 FSP_IP_OPAMP = 38, ///< Operational Amplifier 94 FSP_IP_SDADC = 39, ///< Sigma Delta A/D Converter 95 FSP_IP_RTC = 40, ///< Real Time Clock 96 FSP_IP_WDT = 41, ///< Watch Dog Timer 97 FSP_IP_IWDT = 42, ///< Independent Watch Dog Timer 98 FSP_IP_GPT = 43, ///< General PWM Timer 99 FSP_IP_POEG = 44, ///< Port Output Enable for GPT 100 FSP_IP_OPS = 45, ///< Output Phase Switch 101 FSP_IP_AGT = 47, ///< Asynchronous General-Purpose Timer 102 FSP_IP_CAN = 48, ///< Controller Area Network 103 FSP_IP_IRDA = 49, ///< Infrared Data Association 104 FSP_IP_QSPI = 50, ///< Quad Serial Peripheral Interface 105 FSP_IP_USBFS = 51, ///< USB Full Speed 106 FSP_IP_SDHI = 52, ///< SD/MMC Host Interface 107 FSP_IP_SRC = 53, ///< Sampling Rate Converter 108 FSP_IP_SSI = 54, ///< Serial Sound Interface 109 FSP_IP_DALI = 55, ///< Digital Addressable Lighting Interface 110 FSP_IP_ETHER = 64, ///< Ethernet MAC Controller 111 FSP_IP_EDMAC = 64, ///< Ethernet DMA Controller 112 FSP_IP_EPTPC = 65, ///< Ethernet PTP Controller 113 FSP_IP_PDC = 66, ///< Parallel Data Capture Unit 114 FSP_IP_GLCDC = 67, ///< Graphics LCD Controller 115 FSP_IP_DRW = 68, ///< 2D Drawing Engine 116 FSP_IP_JPEG = 69, ///< JPEG 117 FSP_IP_DAC8 = 70, ///< 8-Bit D/A Converter 118 FSP_IP_USBHS = 71, ///< USB High Speed 119 FSP_IP_OSPI = 72, ///< Octa Serial Peripheral Interface 120 FSP_IP_CEC = 73, ///< HDMI CEC 121 FSP_IP_TFU = 74, ///< Trigonometric Function Unit 122 FSP_IP_IIRFA = 75, ///< IIR Filter Accelerator 123 FSP_IP_CANFD = 76, ///< CAN-FD 124 FSP_IP_ULPT = 77, ///< Ultra Low Power Timer ULPT 125 } fsp_ip_t; 126 127 /** Signals that can be mapped to an interrupt. */ 128 typedef enum e_fsp_signal 129 { 130 FSP_SIGNAL_ADC_COMPARE_MATCH = 0, ///< ADC COMPARE MATCH 131 FSP_SIGNAL_ADC_COMPARE_MISMATCH, ///< ADC COMPARE MISMATCH 132 FSP_SIGNAL_ADC_SCAN_END, ///< ADC SCAN END 133 FSP_SIGNAL_ADC_SCAN_END_B, ///< ADC SCAN END B 134 FSP_SIGNAL_ADC_WINDOW_A, ///< ADC WINDOW A 135 FSP_SIGNAL_ADC_WINDOW_B, ///< ADC WINDOW B 136 FSP_SIGNAL_AES_RDREQ = 0, ///< AES RDREQ 137 FSP_SIGNAL_AES_WRREQ, ///< AES WRREQ 138 FSP_SIGNAL_AGT_COMPARE_A = 0, ///< AGT COMPARE A 139 FSP_SIGNAL_AGT_COMPARE_B, ///< AGT COMPARE B 140 FSP_SIGNAL_AGT_INT, ///< AGT INT 141 FSP_SIGNAL_CAC_FREQUENCY_ERROR = 0, ///< CAC FREQUENCY ERROR 142 FSP_SIGNAL_CAC_MEASUREMENT_END, ///< CAC MEASUREMENT END 143 FSP_SIGNAL_CAC_OVERFLOW, ///< CAC OVERFLOW 144 FSP_SIGNAL_CAN_ERROR = 0, ///< CAN ERROR 145 FSP_SIGNAL_CAN_FIFO_RX, ///< CAN FIFO RX 146 FSP_SIGNAL_CAN_FIFO_TX, ///< CAN FIFO TX 147 FSP_SIGNAL_CAN_MAILBOX_RX, ///< CAN MAILBOX RX 148 FSP_SIGNAL_CAN_MAILBOX_TX, ///< CAN MAILBOX TX 149 FSP_SIGNAL_CGC_MOSC_STOP = 0, ///< CGC MOSC STOP 150 FSP_SIGNAL_LPM_SNOOZE_REQUEST, ///< LPM SNOOZE REQUEST 151 FSP_SIGNAL_LVD_LVD1, ///< LVD LVD1 152 FSP_SIGNAL_LVD_LVD2, ///< LVD LVD2 153 FSP_SIGNAL_VBATT_LVD, ///< VBATT LVD 154 FSP_SIGNAL_LVD_VBATT = FSP_SIGNAL_VBATT_LVD, ///< LVD VBATT 155 FSP_SIGNAL_ACMPHS_INT = 0, ///< ACMPHS INT 156 FSP_SIGNAL_ACMPLP_INT = 0, ///< ACMPLP INT 157 FSP_SIGNAL_CTSU_END = 0, ///< CTSU END 158 FSP_SIGNAL_CTSU_READ, ///< CTSU READ 159 FSP_SIGNAL_CTSU_WRITE, ///< CTSU WRITE 160 FSP_SIGNAL_DALI_DEI = 0, ///< DALI DEI 161 FSP_SIGNAL_DALI_CLI, ///< DALI CLI 162 FSP_SIGNAL_DALI_SDI, ///< DALI SDI 163 FSP_SIGNAL_DALI_BPI, ///< DALI BPI 164 FSP_SIGNAL_DALI_FEI, ///< DALI FEI 165 FSP_SIGNAL_DALI_SDI_OR_BPI, ///< DALI SDI OR BPI 166 FSP_SIGNAL_DMAC_INT = 0, ///< DMAC INT 167 FSP_SIGNAL_DOC_INT = 0, ///< DOC INT 168 FSP_SIGNAL_DRW_INT = 0, ///< DRW INT 169 FSP_SIGNAL_DTC_COMPLETE = 0, ///< DTC COMPLETE 170 FSP_SIGNAL_DTC_END, ///< DTC END 171 FSP_SIGNAL_EDMAC_EINT = 0, ///< EDMAC EINT 172 FSP_SIGNAL_ELC_SOFTWARE_EVENT_0 = 0, ///< ELC SOFTWARE EVENT 0 173 FSP_SIGNAL_ELC_SOFTWARE_EVENT_1, ///< ELC SOFTWARE EVENT 1 174 FSP_SIGNAL_EPTPC_IPLS = 0, ///< EPTPC IPLS 175 FSP_SIGNAL_EPTPC_MINT, ///< EPTPC MINT 176 FSP_SIGNAL_EPTPC_PINT, ///< EPTPC PINT 177 FSP_SIGNAL_EPTPC_TIMER0_FALL, ///< EPTPC TIMER0 FALL 178 FSP_SIGNAL_EPTPC_TIMER0_RISE, ///< EPTPC TIMER0 RISE 179 FSP_SIGNAL_EPTPC_TIMER1_FALL, ///< EPTPC TIMER1 FALL 180 FSP_SIGNAL_EPTPC_TIMER1_RISE, ///< EPTPC TIMER1 RISE 181 FSP_SIGNAL_EPTPC_TIMER2_FALL, ///< EPTPC TIMER2 FALL 182 FSP_SIGNAL_EPTPC_TIMER2_RISE, ///< EPTPC TIMER2 RISE 183 FSP_SIGNAL_EPTPC_TIMER3_FALL, ///< EPTPC TIMER3 FALL 184 FSP_SIGNAL_EPTPC_TIMER3_RISE, ///< EPTPC TIMER3 RISE 185 FSP_SIGNAL_EPTPC_TIMER4_FALL, ///< EPTPC TIMER4 FALL 186 FSP_SIGNAL_EPTPC_TIMER4_RISE, ///< EPTPC TIMER4 RISE 187 FSP_SIGNAL_EPTPC_TIMER5_FALL, ///< EPTPC TIMER5 FALL 188 FSP_SIGNAL_EPTPC_TIMER5_RISE, ///< EPTPC TIMER5 RISE 189 FSP_SIGNAL_FCU_FIFERR = 0, ///< FCU FIFERR 190 FSP_SIGNAL_FCU_FRDYI, ///< FCU FRDYI 191 FSP_SIGNAL_GLCDC_LINE_DETECT = 0, ///< GLCDC LINE DETECT 192 FSP_SIGNAL_GLCDC_UNDERFLOW_1, ///< GLCDC UNDERFLOW 1 193 FSP_SIGNAL_GLCDC_UNDERFLOW_2, ///< GLCDC UNDERFLOW 2 194 FSP_SIGNAL_GPT_CAPTURE_COMPARE_A = 0, ///< GPT CAPTURE COMPARE A 195 FSP_SIGNAL_GPT_CAPTURE_COMPARE_B, ///< GPT CAPTURE COMPARE B 196 FSP_SIGNAL_GPT_COMPARE_C, ///< GPT COMPARE C 197 FSP_SIGNAL_GPT_COMPARE_D, ///< GPT COMPARE D 198 FSP_SIGNAL_GPT_COMPARE_E, ///< GPT COMPARE E 199 FSP_SIGNAL_GPT_COMPARE_F, ///< GPT COMPARE F 200 FSP_SIGNAL_GPT_COUNTER_OVERFLOW, ///< GPT COUNTER OVERFLOW 201 FSP_SIGNAL_GPT_COUNTER_UNDERFLOW, ///< GPT COUNTER UNDERFLOW 202 FSP_SIGNAL_GPT_AD_TRIG_A, ///< GPT AD TRIG A 203 FSP_SIGNAL_GPT_AD_TRIG_B, ///< GPT AD TRIG B 204 FSP_SIGNAL_OPS_UVW_EDGE, ///< OPS UVW EDGE 205 FSP_SIGNAL_ICU_IRQ0 = 0, ///< ICU IRQ0 206 FSP_SIGNAL_ICU_IRQ1, ///< ICU IRQ1 207 FSP_SIGNAL_ICU_IRQ2, ///< ICU IRQ2 208 FSP_SIGNAL_ICU_IRQ3, ///< ICU IRQ3 209 FSP_SIGNAL_ICU_IRQ4, ///< ICU IRQ4 210 FSP_SIGNAL_ICU_IRQ5, ///< ICU IRQ5 211 FSP_SIGNAL_ICU_IRQ6, ///< ICU IRQ6 212 FSP_SIGNAL_ICU_IRQ7, ///< ICU IRQ7 213 FSP_SIGNAL_ICU_IRQ8, ///< ICU IRQ8 214 FSP_SIGNAL_ICU_IRQ9, ///< ICU IRQ9 215 FSP_SIGNAL_ICU_IRQ10, ///< ICU IRQ10 216 FSP_SIGNAL_ICU_IRQ11, ///< ICU IRQ11 217 FSP_SIGNAL_ICU_IRQ12, ///< ICU IRQ12 218 FSP_SIGNAL_ICU_IRQ13, ///< ICU IRQ13 219 FSP_SIGNAL_ICU_IRQ14, ///< ICU IRQ14 220 FSP_SIGNAL_ICU_IRQ15, ///< ICU IRQ15 221 FSP_SIGNAL_ICU_SNOOZE_CANCEL, ///< ICU SNOOZE CANCEL 222 FSP_SIGNAL_IIC_ERI = 0, ///< IIC ERI 223 FSP_SIGNAL_IIC_RXI, ///< IIC RXI 224 FSP_SIGNAL_IIC_TEI, ///< IIC TEI 225 FSP_SIGNAL_IIC_TXI, ///< IIC TXI 226 FSP_SIGNAL_IIC_WUI, ///< IIC WUI 227 FSP_SIGNAL_IOPORT_EVENT_1 = 0, ///< IOPORT EVENT 1 228 FSP_SIGNAL_IOPORT_EVENT_2, ///< IOPORT EVENT 2 229 FSP_SIGNAL_IOPORT_EVENT_3, ///< IOPORT EVENT 3 230 FSP_SIGNAL_IOPORT_EVENT_4, ///< IOPORT EVENT 4 231 FSP_SIGNAL_IOPORT_EVENT_B = 0, ///< IOPORT EVENT B 232 FSP_SIGNAL_IOPORT_EVENT_C, ///< IOPORT EVENT C 233 FSP_SIGNAL_IOPORT_EVENT_D, ///< IOPORT EVENT D 234 FSP_SIGNAL_IOPORT_EVENT_E, ///< IOPORT EVENT E 235 FSP_SIGNAL_IWDT_UNDERFLOW = 0, ///< IWDT UNDERFLOW 236 FSP_SIGNAL_JPEG_JDTI = 0, ///< JPEG JDTI 237 FSP_SIGNAL_JPEG_JEDI, ///< JPEG JEDI 238 FSP_SIGNAL_KEY_INT = 0, ///< KEY INT 239 FSP_SIGNAL_PDC_FRAME_END = 0, ///< PDC FRAME END 240 FSP_SIGNAL_PDC_INT, ///< PDC INT 241 FSP_SIGNAL_PDC_RECEIVE_DATA_READY, ///< PDC RECEIVE DATA READY 242 FSP_SIGNAL_POEG_EVENT = 0, ///< POEG EVENT 243 FSP_SIGNAL_QSPI_INT = 0, ///< QSPI INT 244 FSP_SIGNAL_RTC_ALARM = 0, ///< RTC ALARM 245 FSP_SIGNAL_RTC_PERIOD, ///< RTC PERIOD 246 FSP_SIGNAL_RTC_CARRY, ///< RTC CARRY 247 FSP_SIGNAL_SCE_INTEGRATE_RDRDY = 0, ///< SCE INTEGRATE RDRDY 248 FSP_SIGNAL_SCE_INTEGRATE_WRRDY, ///< SCE INTEGRATE WRRDY 249 FSP_SIGNAL_SCE_LONG_PLG, ///< SCE LONG PLG 250 FSP_SIGNAL_SCE_PROC_BUSY, ///< SCE PROC BUSY 251 FSP_SIGNAL_SCE_RDRDY_0, ///< SCE RDRDY 0 252 FSP_SIGNAL_SCE_RDRDY_1, ///< SCE RDRDY 1 253 FSP_SIGNAL_SCE_ROMOK, ///< SCE ROMOK 254 FSP_SIGNAL_SCE_TEST_BUSY, ///< SCE TEST BUSY 255 FSP_SIGNAL_SCE_WRRDY_0, ///< SCE WRRDY 0 256 FSP_SIGNAL_SCE_WRRDY_1, ///< SCE WRRDY 1 257 FSP_SIGNAL_SCE_WRRDY_4, ///< SCE WRRDY 4 258 FSP_SIGNAL_SCI_AM = 0, ///< SCI AM 259 FSP_SIGNAL_SCI_ERI, ///< SCI ERI 260 FSP_SIGNAL_SCI_RXI, ///< SCI RXI 261 FSP_SIGNAL_SCI_RXI_OR_ERI, ///< SCI RXI OR ERI 262 FSP_SIGNAL_SCI_TEI, ///< SCI TEI 263 FSP_SIGNAL_SCI_TXI, ///< SCI TXI 264 FSP_SIGNAL_SDADC_ADI = 0, ///< SDADC ADI 265 FSP_SIGNAL_SDADC_SCANEND, ///< SDADC SCANEND 266 FSP_SIGNAL_SDADC_CALIEND, ///< SDADC CALIEND 267 FSP_SIGNAL_SDHIMMC_ACCS = 0, ///< SDHIMMC ACCS 268 FSP_SIGNAL_SDHIMMC_CARD, ///< SDHIMMC CARD 269 FSP_SIGNAL_SDHIMMC_DMA_REQ, ///< SDHIMMC DMA REQ 270 FSP_SIGNAL_SDHIMMC_SDIO, ///< SDHIMMC SDIO 271 FSP_SIGNAL_SPI_ERI = 0, ///< SPI ERI 272 FSP_SIGNAL_SPI_IDLE, ///< SPI IDLE 273 FSP_SIGNAL_SPI_RXI, ///< SPI RXI 274 FSP_SIGNAL_SPI_TEI, ///< SPI TEI 275 FSP_SIGNAL_SPI_TXI, ///< SPI TXI 276 FSP_SIGNAL_SRC_CONVERSION_END = 0, ///< SRC CONVERSION END 277 FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY, ///< SRC INPUT FIFO EMPTY 278 FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL, ///< SRC OUTPUT FIFO FULL 279 FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW, ///< SRC OUTPUT FIFO OVERFLOW 280 FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW, ///< SRC OUTPUT FIFO UNDERFLOW 281 FSP_SIGNAL_SSI_INT = 0, ///< SSI INT 282 FSP_SIGNAL_SSI_RXI, ///< SSI RXI 283 FSP_SIGNAL_SSI_TXI, ///< SSI TXI 284 FSP_SIGNAL_SSI_TXI_RXI, ///< SSI TXI RXI 285 FSP_SIGNAL_TRNG_RDREQ = 0, ///< TRNG RDREQ 286 FSP_SIGNAL_USB_FIFO_0 = 0, ///< USB FIFO 0 287 FSP_SIGNAL_USB_FIFO_1, ///< USB FIFO 1 288 FSP_SIGNAL_USB_INT, ///< USB INT 289 FSP_SIGNAL_USB_RESUME, ///< USB RESUME 290 FSP_SIGNAL_USB_USB_INT_RESUME, ///< USB USB INT RESUME 291 FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW 292 FSP_SIGNAL_ULPT_COMPARE_A = 0, ///< ULPT COMPARE A 293 FSP_SIGNAL_ULPT_COMPARE_B, ///< ULPT COMPARE B 294 FSP_SIGNAL_ULPT_INT, ///< ULPT INT 295 } fsp_signal_t; 296 297 typedef void (* fsp_vector_t)(void); 298 299 /** @} (end addtogroup BSP_MCU) */ 300 301 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 302 FSP_FOOTER 303 304 #endif 305