1 /*********************************************************************************************************************** 2 * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. 3 * 4 * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products 5 * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are 6 * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use 7 * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property 8 * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas 9 * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION 10 * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT 11 * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES 12 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR 13 * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM 14 * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION 15 * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, 16 * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, 17 * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY 18 * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. 19 **********************************************************************************************************************/ 20 21 #ifndef R_SCI_B_UART_H 22 #define R_SCI_B_UART_H 23 24 /*******************************************************************************************************************//** 25 * @addtogroup SCI_B_UART 26 * @{ 27 **********************************************************************************************************************/ 28 29 /*********************************************************************************************************************** 30 * Includes 31 **********************************************************************************************************************/ 32 #include "bsp_api.h" 33 #include "r_uart_api.h" 34 #include "r_sci_b_uart_cfg.h" 35 36 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 37 FSP_HEADER 38 39 /*********************************************************************************************************************** 40 * Macro definitions 41 **********************************************************************************************************************/ 42 43 /********************************************************************************************************************** 44 * Typedef definitions 45 **********************************************************************************************************************/ 46 47 /** Enumeration for SCI clock source */ 48 typedef enum e_sci_b_clk_src 49 { 50 SCI_B_UART_CLOCK_INT, ///< Use internal clock for baud generation 51 SCI_B_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, ///< Use internal clock for baud generation and output on SCK 52 SCI_B_UART_CLOCK_EXT8X, ///< Use external clock 8x baud rate 53 SCI_B_UART_CLOCK_EXT16X ///< Use external clock 16x baud rate 54 } sci_b_clk_src_t; 55 56 /** UART flow control mode definition */ 57 typedef enum e_sci_b_uart_flow_control 58 { 59 SCI_B_UART_FLOW_CONTROL_RTS = 0U, ///< Use CTSn_RTSn pin for RTS 60 SCI_B_UART_FLOW_CONTROL_CTS = 1U, ///< Use CTSn_RTSn pin for CTS 61 SCI_B_UART_FLOW_CONTROL_HARDWARE_CTSRTS = 3U, ///< Use CTSn pin for CTS, CTSn_RTSn pin for RTS 62 SCI_B_UART_FLOW_CONTROL_CTSRTS = 5U, ///< Use SCI pin for CTS, external pin for RTS 63 } sci_b_uart_flow_control_t; 64 65 /** UART instance control block. */ 66 typedef struct st_sci_b_uart_instance_ctrl 67 { 68 /* Parameters to control UART peripheral device */ 69 uint8_t fifo_depth; // FIFO depth of the UART channel 70 uint8_t rx_transfer_in_progress; // Set to 1 if a receive transfer is in progress, 0 otherwise 71 uint8_t data_bytes : 2; // 1 byte for 7 or 8 bit data, 2 bytes for 9 bit data 72 uint8_t bitrate_modulation : 1; // 1 if bit rate modulation is enabled, 0 otherwise 73 uint32_t open; // Used to determine if the channel is configured 74 75 bsp_io_port_pin_t flow_pin; 76 77 /* Source buffer pointer used to fill hardware FIFO from transmit ISR. */ 78 uint8_t const * p_tx_src; 79 80 /* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */ 81 uint32_t tx_src_bytes; 82 83 /* Destination buffer pointer used for receiving data. */ 84 uint8_t const * p_rx_dest; 85 86 /* Size of destination buffer pointer used for receiving data. */ 87 uint32_t rx_dest_bytes; 88 89 /* Pointer to the configuration block. */ 90 uart_cfg_t const * p_cfg; 91 92 /* Base register for this channel */ 93 R_SCI_B0_Type * p_reg; 94 95 void (* p_callback)(uart_callback_args_t *); // Pointer to callback that is called when a uart_event_t occurs. 96 uart_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. 97 98 /* Pointer to context to be passed into callback function */ 99 void const * p_context; 100 } sci_b_uart_instance_ctrl_t; 101 102 /** Receive FIFO trigger configuration. */ 103 typedef enum e_sci_b_uart_rx_fifo_trigger 104 { 105 SCI_B_UART_RX_FIFO_TRIGGER_1 = 0x1, ///< Callback after each byte is received without buffering 106 SCI_B_UART_RX_FIFO_TRIGGER_MAX = 0xF, ///< Callback when FIFO is full or after 15 bit times with no data (fewer interrupts) 107 } sci_b_uart_rx_fifo_trigger_t; 108 109 /** Asynchronous Start Bit Edge Detection configuration. */ 110 typedef enum e_sci_b_uart_start_bit_detect 111 { 112 SCI_B_UART_START_BIT_LOW_LEVEL = 0x0, ///< Detect low level on RXDn pin as start bit 113 SCI_B_UART_START_BIT_FALLING_EDGE = 0x1, ///< Detect falling level on RXDn pin as start bit 114 } sci_b_uart_start_bit_detect_t; 115 116 /** Noise cancellation configuration. */ 117 typedef enum e_sci_b_uart_noise_cancellation 118 { 119 SCI_B_UART_NOISE_CANCELLATION_DISABLE = 0x0, ///< Disable noise cancellation 120 SCI_B_UART_NOISE_CANCELLATION_ENABLE = 0x1, ///< Enable noise cancellation 121 } sci_b_uart_noise_cancellation_t; 122 123 /** RS-485 Enable/Disable. */ 124 typedef enum e_sci_b_uart_rs485_enable 125 { 126 SCI_B_UART_RS485_DISABLE = 0, ///< RS-485 disabled. 127 SCI_B_UART_RS485_ENABLE = 1, ///< RS-485 enabled. 128 } sci_b_uart_rs485_enable_t; 129 130 /** The polarity of the RS-485 DE signal. */ 131 typedef enum e_sci_b_uart_rs485_de_polarity 132 { 133 SCI_B_UART_RS485_DE_POLARITY_HIGH = 0, ///< The DE signal is high when a write transfer is in progress. 134 SCI_B_UART_RS485_DE_POLARITY_LOW = 1, ///< The DE signal is low when a write transfer is in progress. 135 } sci_b_uart_rs485_de_polarity_t; 136 137 /** Register settings to acheive a desired baud rate and modulation duty. */ 138 typedef struct st_sci_b_baud_setting_t 139 { 140 union 141 { 142 uint32_t baudrate_bits; 143 144 struct 145 { 146 uint32_t : 3; 147 uint32_t : 1; 148 uint32_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select 149 uint32_t abcs : 1; ///< Asynchronous Mode Base Clock Select 150 uint32_t abcse : 1; ///< Asynchronous Mode Extended Base Clock Select 1 151 uint32_t : 1; 152 uint32_t brr : 8; ///< Bit Rate Register setting 153 uint32_t brme : 1; ///< Bit Rate Modulation Enable 154 uint32_t : 3; 155 uint32_t cks : 2; ///< CKS value to get divisor (CKS = N) 156 uint32_t : 2; 157 uint32_t mddr : 8; ///< Modulation Duty Register setting 158 } baudrate_bits_b; 159 }; 160 } sci_b_baud_setting_t; 161 162 /** Configuration settings for controlling the DE signal for RS-485. */ 163 typedef struct st_sci_b_uart_rs485_setting 164 { 165 sci_b_uart_rs485_enable_t enable; ///< Enable the DE signal. 166 sci_b_uart_rs485_de_polarity_t polarity; ///< DE signal polarity. 167 uint8_t assertion_time : 5; ///< Time in baseclock units after assertion of the DE signal and before the start of the write transfer. 168 uint8_t negation_time : 5; ///< Time in baseclock units after the end of a write transfer and before the DE signal is negated. 169 } sci_b_uart_rs485_setting_t; 170 171 /** UART on SCI device Configuration */ 172 typedef struct st_sci_b_uart_extended_cfg 173 { 174 sci_b_clk_src_t clock; ///< The source clock for the baud-rate generator. If internal optionally output baud rate on SCK 175 sci_b_uart_start_bit_detect_t rx_edge_start; ///< Start reception on falling edge 176 sci_b_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting 177 sci_b_baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate. 178 sci_b_uart_rx_fifo_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level, unused if channel has no FIFO or if DTC is used. 179 bsp_io_port_pin_t flow_control_pin; ///< UART Driver Enable pin 180 sci_b_uart_flow_control_t flow_control; ///< CTS/RTS function of the SSn pin 181 sci_b_uart_rs485_setting_t rs485_setting; ///< RS-485 settings. 182 } sci_b_uart_extended_cfg_t; 183 184 /********************************************************************************************************************** 185 * Exported global variables 186 **********************************************************************************************************************/ 187 188 /** @cond INC_HEADER_DEFS_SEC */ 189 /** Filled in Interface API structure for this Instance. */ 190 extern const uart_api_t g_uart_on_sci_b; 191 192 /** @endcond */ 193 194 fsp_err_t R_SCI_B_UART_Open(uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg); 195 fsp_err_t R_SCI_B_UART_Read(uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes); 196 fsp_err_t R_SCI_B_UART_Write(uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes); 197 fsp_err_t R_SCI_B_UART_BaudSet(uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting); 198 fsp_err_t R_SCI_B_UART_InfoGet(uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info); 199 fsp_err_t R_SCI_B_UART_Close(uart_ctrl_t * const p_api_ctrl); 200 fsp_err_t R_SCI_B_UART_Abort(uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort); 201 fsp_err_t R_SCI_B_UART_BaudCalculate(uint32_t baudrate, 202 bool bitrate_modulation, 203 uint32_t baud_rate_error_x_1000, 204 sci_b_baud_setting_t * const p_baud_setting); 205 fsp_err_t R_SCI_B_UART_CallbackSet(uart_ctrl_t * const p_api_ctrl, 206 void ( * p_callback)(uart_callback_args_t *), 207 void const * const p_context, 208 uart_callback_args_t * const p_callback_memory); 209 fsp_err_t R_SCI_B_UART_ReadStop(uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes); 210 211 /*******************************************************************************************************************//** 212 * @} (end addtogroup SCI_B_UART) 213 **********************************************************************************************************************/ 214 215 /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 216 FSP_FOOTER 217 218 #endif 219