1<?xml version="1.0" encoding="UTF-8" standalone="no"?> 2<raConfiguration version="9"> 3 <generalSettings> 4 <option key="#Board#" value="board.rzn2lrsk.xspi0_x1"/> 5 <option key="CPU" value="RZN2L"/> 6 <option key="Core" value="CR52_0"/> 7 <option key="#TargetName#" value="R9A07G084M04GBG"/> 8 <option key="#TargetARCHITECTURE#" value="cortex-r52"/> 9 <option key="#DeviceCommand#" value="R9A07G084M04"/> 10 <option key="#RTOS#" value="_none"/> 11 <option key="#pinconfiguration#" value="R9A07G084M04GBG.pincfg"/> 12 <option key="#FSPVersion#" value="2.0.0"/> 13 <option key="#ConfigurationFragments#" value="Renesas##BSP##Board##rzn2l_rsk##xspi0_x1_boot"/> 14 <option key="#SELECTED_TOOLCHAIN#" value="iar.arm.toolchain"/> 15 </generalSettings> 16 <raBspConfiguration/> 17 <raClockConfiguration> 18 <node id="board.clock.main.freq" option="board.clock.main.freq.25m"/> 19 <node id="board.clock.loco.enable" option="board.clock.loco.enable.enabled"/> 20 <node id="board.clock.pll0.display" option="board.clock.pll0.display.value"/> 21 <node id="board.clock.pll1" option="board.clock.pll1.initial"/> 22 <node id="board.clock.pll1.display" option="board.clock.pll1.display.value"/> 23 <node id="board.clock.ethernet.source" option="board.clock.ethernet.source.main"/> 24 <node id="board.clock.reference.display" option="board.clock.reference.display.value"/> 25 <node id="board.clock.loco.freq" option="board.clock.loco.freq.240k"/> 26 <node id="board.clock.clma0.enable" option="board.clock.clma0.enable.enabled"/> 27 <node id="board.clock.clma0.error" option="board.clock.clma0.error.not_mask"/> 28 <node id="board.clock.clma3.error" option="board.clock.clma3.error.not_mask"/> 29 <node id="board.clock.clma1.error" option="board.clock.clma1.error.mask"/> 30 <node id="board.clock.clma3.enable" option="board.clock.clma3.enable.enabled"/> 31 <node id="board.clock.clma1.enable" option="board.clock.clma1.enable.enabled"/> 32 <node id="board.clock.clma2.enable" option="board.clock.clma2.enable.enabled"/> 33 <node id="board.clock.clma0.cmpl" mul="1" option="_edit"/> 34 <node id="board.clock.clma1.cmpl" mul="1" option="_edit"/> 35 <node id="board.clock.clma2.cmpl" mul="1" option="_edit"/> 36 <node id="board.clock.clma3.cmpl" mul="1" option="_edit"/> 37 <node id="board.clock.alternative.source" option="board.clock.alternative.source.loco"/> 38 <node id="board.clock.clma0.cmph" mul="1023" option="_edit"/> 39 <node id="board.clock.clma1.cmph" mul="1023" option="_edit"/> 40 <node id="board.clock.clma2.cmph" mul="1023" option="_edit"/> 41 <node id="board.clock.clma3.cmph" mul="1023" option="_edit"/> 42 <node id="board.clock.iclk.freq" option="board.clock.iclk.freq.200m"/> 43 <node id="board.clock.cpu0clk.mul" option="board.clock.cpu0clk.mul.2"/> 44 <node id="board.clock.cpu0clk.display" option="board.clock.cpu0clk.display.value"/> 45 <node id="board.clock.ckio.div" option="board.clock.ckio.div.4"/> 46 <node id="board.clock.ckio.display" option="board.clock.ckio.display.value"/> 47 <node id="board.clock.sci0asyncclk.sel" option="board.clock.sci0asyncclk.sel.1"/> 48 <node id="board.clock.sci1asyncclk.sel" option="board.clock.sci1asyncclk.sel.1"/> 49 <node id="board.clock.sci2asyncclk.sel" option="board.clock.sci2asyncclk.sel.1"/> 50 <node id="board.clock.sci3asyncclk.sel" option="board.clock.sci3asyncclk.sel.1"/> 51 <node id="board.clock.sci4asyncclk.sel" option="board.clock.sci4asyncclk.sel.1"/> 52 <node id="board.clock.sci5asyncclk.sel" option="board.clock.sci5asyncclk.sel.1"/> 53 <node id="board.clock.spi0asyncclk.sel" option="board.clock.spi0asyncclk.sel.1"/> 54 <node id="board.clock.spi1asyncclk.sel" option="board.clock.spi1asyncclk.sel.1"/> 55 <node id="board.clock.spi2asyncclk.sel" option="board.clock.spi2asyncclk.sel.1"/> 56 <node id="board.clock.spi3asyncclk.sel" option="board.clock.spi3asyncclk.sel.1"/> 57 <node id="board.clock.pclkshost.display" option="board.clock.pclkshost.display.value"/> 58 <node id="board.clock.pclkgptl.display" option="board.clock.pclkgptl.display.value"/> 59 <node id="board.clock.pclkh.display" option="board.clock.pclkh.display.value"/> 60 <node id="board.clock.pclkm.display" option="board.clock.pclkm.display.value"/> 61 <node id="board.clock.pclkl.display" option="board.clock.pclkl.display.value"/> 62 <node id="board.clock.pclkadc.display" option="board.clock.pclkadc.display.value"/> 63 <node id="board.clock.pclkcan.freq" option="board.clock.pclkcan.freq.40m"/> 64 <node id="board.clock.xspi.clk0.freq" option="board.clock.xspi.clk0.freq.133m"/> 65 <node id="board.clock.xspi.clk1.freq" option="board.clock.xspi.clk1.freq.12m"/> 66 <node id="board.clock.tclk.freq" option="board.clock.tclk.freq.100m"/> 67 </raClockConfiguration> 68 <raPinConfiguration> 69 <pincfg active="true" name="" symbol=""> 70 <configSetting altId="jtag_fslash_swd.tck_swclk.p02_7" configurationId="jtag_fslash_swd.tck_swclk" isUsedByDriver="true"/> 71 <configSetting altId="jtag_fslash_swd.tdi.p02_5" configurationId="jtag_fslash_swd.tdi" isUsedByDriver="true"/> 72 <configSetting altId="jtag_fslash_swd.tdo.p02_4" configurationId="jtag_fslash_swd.tdo" isUsedByDriver="true"/> 73 <configSetting altId="jtag_fslash_swd.tms_swdio.p02_6" configurationId="jtag_fslash_swd.tms_swdio" isUsedByDriver="true"/> 74 <configSetting altId="p03_0.output.low" configurationId="p03_0"/> 75 <configSetting altId="p04_1.output.low" configurationId="p04_1"/> 76 <configSetting altId="p04_4.output.low" configurationId="p04_4"/> 77 <configSetting altId="p05_0.output.low" configurationId="p05_0"/> 78 <configSetting altId="p05_4.input" configurationId="p05_4"/> 79 <configSetting altId="p13_4.output.low" configurationId="p13_4"/> 80 <configSetting altId="p13_5.input" configurationId="p13_5"/> 81 <configSetting altId="p13_6.input" configurationId="p13_6"/> 82 <configSetting altId="p13_7.input" configurationId="p13_7"/> 83 <configSetting altId="p14_0.output.low" configurationId="p14_0"/> 84 <configSetting altId="p14_1.output.low" configurationId="p14_1"/> 85 <configSetting altId="p14_3.output.low" configurationId="p14_3"/> 86 <configSetting altId="p16_3.input" configurationId="p16_3"/> 87 <configSetting altId="p17_3.output.low" configurationId="p17_3"/> 88 <configSetting altId="p18_2.output.low" configurationId="p18_2"/> 89 <configSetting altId="p22_1.output.low" configurationId="p22_1"/> 90 <configSetting altId="p22_3.output.low" configurationId="p22_3"/> 91 <configSetting altId="sci0.rxd_miso0.p16_6" configurationId="sci0.rxd_miso0" isUsedByDriver="true"/> 92 <configSetting altId="sci0.txd_mosi0.p16_5" configurationId="sci0.txd_mosi0" isUsedByDriver="true"/> 93 <configSetting altId="xspi0.xspi0_ckn.p14_5" configurationId="xspi0.xspi0_ckn"/> 94 <configSetting altId="xspi0.xspi0_ckp.p14_6" configurationId="xspi0.xspi0_ckp"/> 95 <configSetting altId="xspi0.xspi0_cs0_hash.p15_7" configurationId="xspi0.xspi0_cs0_hash"/> 96 <configSetting altId="xspi0.xspi0_cs1_hash.p16_0" configurationId="xspi0.xspi0_cs1_hash"/> 97 <configSetting altId="xspi0.xspi0_ds.p14_4" configurationId="xspi0.xspi0_ds"/> 98 <configSetting altId="xspi0.xspi0_ecs0_hash.p14_2" configurationId="xspi0.xspi0_ecs0_hash"/> 99 <configSetting altId="xspi0.xspi0_io0.p14_7" configurationId="xspi0.xspi0_io0"/> 100 <configSetting altId="xspi0.xspi0_io1.p15_0" configurationId="xspi0.xspi0_io1"/> 101 <configSetting altId="xspi0.xspi0_io2.p15_1" configurationId="xspi0.xspi0_io2"/> 102 <configSetting altId="xspi0.xspi0_io3.p15_2" configurationId="xspi0.xspi0_io3"/> 103 <configSetting altId="xspi0.xspi0_io4.p15_3" configurationId="xspi0.xspi0_io4"/> 104 <configSetting altId="xspi0.xspi0_io5.p15_4" configurationId="xspi0.xspi0_io5"/> 105 <configSetting altId="xspi0.xspi0_io6.p15_5" configurationId="xspi0.xspi0_io6"/> 106 <configSetting altId="xspi0.xspi0_io7.p15_6" configurationId="xspi0.xspi0_io7"/> 107 <configSetting altId="xspi0.xspi0_reset0_hash.p16_1" configurationId="xspi0.xspi0_reset0_hash"/> 108 </pincfg> 109 </raPinConfiguration> 110</raConfiguration> 111