1 /*
2  * Copyright (c) 2006-2021, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2024-03-11    Wangyuqiang   first version
9  */
10 
11 #ifndef __BOARD_H__
12 #define __BOARD_H__
13 
14 #ifdef __cplusplus
15 extern "C" {
16 #endif
17 
18 #include <rtdef.h>
19 #include <cp15.h>
20 #include <hal_data.h>
21 
22 #define RZ_SRAM_SIZE    1536 /* The SRAM size of the chip needs to be modified */
23 #define RZ_SRAM_END     (0x10000000 + RZ_SRAM_SIZE * 1024 - 1)
24 
25 #ifdef __ARMCC_VERSION
26 extern int Image$$RAM_END$$ZI$$Base;
27 #define HEAP_BEGIN  ((void *)&Image$$RAM_END$$ZI$$Base)
28 #elif __ICCARM__
29 #pragma section="CSTACK"
30 #define HEAP_BEGIN      (__segment_end("CSTACK"))
31 #else
32 extern int __bss_end__;
33 #define HEAP_BEGIN      ((void *)&__bss_end__)
34 #endif
35 
36 #define HEAP_END        RZ_SRAM_END
37 
38 /***********************************************************************************************************************
39  * Macro definitions
40  **********************************************************************************************************************/
41 #define MAX_HANDLERS BSP_VECTOR_TABLE_MAX_ENTRIES
42 #define GIC_IRQ_START   0
43 #define GIC_ACK_INTID_MASK  (0x000003FFU)
44 /* number of interrupts on board */
45 #define ARM_GIC_NR_IRQS     (448)
46 /* only one GIC available */
47 #define ARM_GIC_MAX_NR      1
48 /*  end defined */
49 
50 #define GICV3_DISTRIBUTOR_BASE_ADDR     (0x100000)
51 
52 /* the basic constants and interfaces needed by gic */
platform_get_gic_dist_base(void)53 rt_inline rt_uint32_t platform_get_gic_dist_base(void)
54 {
55     rt_uint32_t gic_base;
56 
57     __get_cp(15, 1, gic_base, 15, 3, 0);
58     return gic_base + GICV3_DISTRIBUTOR_BASE_ADDR;
59 }
60 
61 #ifdef __cplusplus
62 }
63 #endif
64 
65 #endif
66