1 /***********************************************************************************************************************
2 * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
3 *
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19 **********************************************************************************************************************/
20
21 #ifndef BSP_IRQ_H
22 #define BSP_IRQ_H
23
24 /***********************************************************************************************************************
25 * Includes <System Includes> , "Project Includes"
26 **********************************************************************************************************************/
27 #if defined(BSP_CFG_CORE_CR52)
28 #include "cr/bsp_irq_core.h"
29 #endif
30
31 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
32 FSP_HEADER
33
34 /***********************************************************************************************************************
35 * Macro definitions
36 **********************************************************************************************************************/
37
38 /***********************************************************************************************************************
39 * Typedef definitions
40 **********************************************************************************************************************/
41
42 /***********************************************************************************************************************
43 * Exported global variables
44 **********************************************************************************************************************/
45
46 /***********************************************************************************************************************
47 * Exported global functions (to be accessed by other files)
48 **********************************************************************************************************************/
49
50 /***********************************************************************************************************************
51 * Inline Functions
52 **********************************************************************************************************************/
53
54 /*******************************************************************************************************************//**
55 * @addtogroup BSP_MCU
56 * @{
57 **********************************************************************************************************************/
58
59 /*******************************************************************************************************************//**
60 * @brief Sets the ISR context associated with the requested IRQ.
61 *
62 * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this
63 * function.
64 * @param[in] p_context ISR context for IRQ.
65 **********************************************************************************************************************/
R_FSP_IsrContextSet(IRQn_Type const irq,void * p_context)66 __STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context)
67 {
68 /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of
69 * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */
70 r_fsp_irq_context_set(irq, p_context);
71 }
72
73 /*******************************************************************************************************************//**
74 * Clear the GIC pending interrupt.
75 *
76 * @param[in] irq Interrupt for which to clear the Pending bit. Note that the enums listed for IRQn_Type are
77 * only those for the Cortex Processor Exceptions Numbers.
78 **********************************************************************************************************************/
R_BSP_IrqClearPending(IRQn_Type irq)79 __STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq)
80 {
81 r_bsp_irq_clear_pending(irq);
82 }
83
84 /*******************************************************************************************************************//**
85 * Get the GIC pending interrupt.
86 *
87 * @param[in] irq Interrupt that gets a pending bit.. Note that the enums listed for IRQn_Type are
88 * only those for the Cortex Processor Exceptions Numbers.
89 *
90 * @return Value indicating the status of the level interrupt.
91 **********************************************************************************************************************/
R_BSP_IrqPendingGet(IRQn_Type irq)92 __STATIC_INLINE uint32_t R_BSP_IrqPendingGet (IRQn_Type irq)
93 {
94 return r_bsp_irq_pending_get(irq);
95 }
96
97 /*******************************************************************************************************************//**
98 * Sets the interrupt priority and context.
99 *
100 * @param[in] irq The IRQ number to configure.
101 * @param[in] priority GIC priority of the interrupt
102 * @param[in] p_context The interrupt context is a pointer to data required in the ISR.
103 **********************************************************************************************************************/
R_BSP_IrqCfg(IRQn_Type const irq,uint32_t priority,void * p_context)104 __STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context)
105 {
106 r_bsp_irq_cfg(irq, priority);
107
108 /* Store the context. The context is recovered in the ISR. */
109 R_FSP_IsrContextSet(irq, p_context);
110 }
111
112 /*******************************************************************************************************************//**
113 * Enable the IRQ in the GIC (Without clearing the pending bit).
114 *
115 * @param[in] irq The IRQ number to enable. Note that the enums listed for IRQn_Type are only those for the
116 * Cortex Processor Exceptions Numbers.
117 **********************************************************************************************************************/
R_BSP_IrqEnableNoClear(IRQn_Type const irq)118 __STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq)
119 {
120 r_bsp_irq_enable_no_clear(irq);
121 }
122
123 /*******************************************************************************************************************//**
124 * Enable the IRQ in the GIC (With clearing the pending bit).
125 *
126 * @param[in] irq The IRQ number to enable. Note that the enums listed for IRQn_Type are only those for the
127 * Cortex Processor Exceptions Numbers.
128 **********************************************************************************************************************/
R_BSP_IrqEnable(IRQn_Type const irq)129 __STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq)
130 {
131 /* Clear pending interrupts in the GIC. */
132 R_BSP_IrqClearPending(irq);
133
134 /* Enable the interrupt in the GIC. */
135 R_BSP_IrqEnableNoClear(irq);
136 }
137
138 /*******************************************************************************************************************//**
139 * Disables interrupts in the GIC.
140 *
141 * @param[in] irq The IRQ number to disable in the GIC. Note that the enums listed for IRQn_Type are
142 * only those for the Cortex Processor Exceptions Numbers.
143 **********************************************************************************************************************/
R_BSP_IrqDisable(IRQn_Type const irq)144 __STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq)
145 {
146 r_bsp_irq_disable(irq);
147 }
148
149 /*******************************************************************************************************************//**
150 * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt.
151 *
152 * @param[in] irq Interrupt number.
153 * @param[in] priority GIC priority of the interrupt
154 * @param[in] p_context The interrupt context is a pointer to data required in the ISR.
155 **********************************************************************************************************************/
R_BSP_IrqCfgEnable(IRQn_Type const irq,uint32_t priority,void * p_context)156 __STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context)
157 {
158 R_BSP_IrqCfg(irq, priority, p_context);
159 R_BSP_IrqEnable(irq);
160 }
161
162 /*******************************************************************************************************************//**
163 * @brief Finds the ISR context associated with the requested IRQ.
164 *
165 * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this
166 * function.
167 * @return ISR context for IRQ.
168 **********************************************************************************************************************/
R_FSP_IsrContextGet(IRQn_Type const irq)169 __STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq)
170 {
171 /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of
172 * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */
173 return gp_renesas_isr_context[irq + BSP_VECTOR_NUM_OFFSET];
174 }
175
176 /*******************************************************************************************************************//**
177 * Sets the interrupt detect type.
178 *
179 * @param[in] irq The IRQ number to configure.
180 * @param[in] detect_type GIC detect type of the interrupt (0 : active-HIGH level, 1 : rising edge-triggerd).
181 **********************************************************************************************************************/
R_BSP_IrqDetectTypeSet(IRQn_Type const irq,uint32_t detect_type)182 __STATIC_INLINE void R_BSP_IrqDetectTypeSet (IRQn_Type const irq, uint32_t detect_type)
183 {
184 r_bsp_irq_detect_type_set(irq, detect_type);
185 }
186
187 /*******************************************************************************************************************//**
188 * Sets the interrupt Group.
189 *
190 * @param[in] irq The IRQ number to configure.
191 * @param[in] interrupt_group GIC interrupt group number ( 0 : FIQ, 1 : IRQ ).
192 **********************************************************************************************************************/
R_BSP_IrqGroupSet(IRQn_Type const irq,uint32_t interrupt_group)193 __STATIC_INLINE void R_BSP_IrqGroupSet (IRQn_Type const irq, uint32_t interrupt_group)
194 {
195 r_bsp_irq_group_set(irq, interrupt_group);
196 }
197
198 /*******************************************************************************************************************//**
199 * Sets the interrupt mask level.
200 *
201 * @param[in] mask_level The interrupt mask level
202 **********************************************************************************************************************/
R_BSP_IrqMaskLevelSet(uint32_t mask_level)203 __STATIC_INLINE void R_BSP_IrqMaskLevelSet (uint32_t mask_level)
204 {
205 FSP_CRITICAL_SECTION_SET_STATE(mask_level << BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT);
206 }
207
208 /*******************************************************************************************************************//**
209 * Gets the interrupt mask level.
210 *
211 * @return Value indicating the interrupt mask level.
212 **********************************************************************************************************************/
R_BSP_IrqMaskLevelGet(void)213 __STATIC_INLINE uint32_t R_BSP_IrqMaskLevelGet (void)
214 {
215 return (uint32_t) ((FSP_CRITICAL_SECTION_GET_CURRENT_STATE() >> BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT) &
216 0x0000001FUL);
217 }
218
219 /** @} (end addtogroup BSP_MCU) */
220
221 /*******************************************************************************************************************//**
222 * @internal
223 * @addtogroup BSP_MCU_PRV Internal BSP Documentation
224 * @ingroup RENESAS_INTERNAL
225 * @{
226 **********************************************************************************************************************/
227
228 /* Public functions defined in bsp.h */
229 void bsp_irq_cfg(void); // Used internally by BSP
230
231 /** @} (end addtogroup BSP_MCU_PRV) */
232
233 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
234 FSP_FOOTER
235
236 #endif
237