1 /***********************************************************************************************************************
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19  **********************************************************************************************************************/
20 
21 #ifndef BSP_RESET_H
22 #define BSP_RESET_H
23 
24 /***********************************************************************************************************************
25  * Includes   <System Includes> , "Project Includes"
26  **********************************************************************************************************************/
27 
28 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
29 FSP_HEADER
30 
31 /***********************************************************************************************************************
32  * Macro definitions
33  **********************************************************************************************************************/
34 
35 /* Key code for writing reset register. */
36 #define BSP_PRV_RESET_KEY              (0x4321A501U)
37 #define BSP_PRV_RESET_RELEASE_KEY      (0x00000000U)
38 
39 /* MRCTL register selection. Bits 16-20 assign values in order for the module control registers (A=0, E=4).
40  * Bit 24 indicates whether MRCTLn register is in the safety region. */
41 #define BSP_RESET_MRCTLA_SELECT        (0x00000000U)
42 #define BSP_RESET_MRCTLE_SELECT        (0x00040000U)
43 #define BSP_RESET_MRCTLI_SELECT        (0x00480000U)
44 
45 /* MRCTL register bit number.  */
46 #define BSP_RESET_MRCTL_BIT0_SHIFT     (0x00000000U)
47 #define BSP_RESET_MRCTL_BIT1_SHIFT     (0x00000001U)
48 #define BSP_RESET_MRCTL_BIT2_SHIFT     (0x00000002U)
49 #define BSP_RESET_MRCTL_BIT3_SHIFT     (0x00000003U)
50 #define BSP_RESET_MRCTL_BIT4_SHIFT     (0x00000004U)
51 #define BSP_RESET_MRCTL_BIT5_SHIFT     (0x00000005U)
52 #define BSP_RESET_MRCTL_BIT6_SHIFT     (0x00000006U)
53 #define BSP_RESET_MRCTL_BIT7_SHIFT     (0x00000007U)
54 #define BSP_RESET_MRCTL_BIT8_SHIFT     (0x00000008U)
55 #define BSP_RESET_MRCTL_BIT9_SHIFT     (0x00000009U)
56 #define BSP_RESET_MRCTL_BIT10_SHIFT    (0x0000000AU)
57 #define BSP_RESET_MRCTL_BIT11_SHIFT    (0x0000000BU)
58 #define BSP_RESET_MRCTL_BIT12_SHIFT    (0x0000000CU)
59 #define BSP_RESET_MRCTL_BIT13_SHIFT    (0x0000000DU)
60 #define BSP_RESET_MRCTL_BIT14_SHIFT    (0x0000000EU)
61 #define BSP_RESET_MRCTL_BIT15_SHIFT    (0x0000000FU)
62 #define BSP_RESET_MRCTL_BIT16_SHIFT    (0x00000010U)
63 #define BSP_RESET_MRCTL_BIT17_SHIFT    (0x00000011U)
64 #define BSP_RESET_MRCTL_BIT18_SHIFT    (0x00000012U)
65 #define BSP_RESET_MRCTL_BIT19_SHIFT    (0x00000013U)
66 #define BSP_RESET_MRCTL_BIT20_SHIFT    (0x00000014U)
67 #define BSP_RESET_MRCTL_BIT21_SHIFT    (0x00000015U)
68 #define BSP_RESET_MRCTL_BIT22_SHIFT    (0x00000016U)
69 #define BSP_RESET_MRCTL_BIT23_SHIFT    (0x00000017U)
70 #define BSP_RESET_MRCTL_BIT24_SHIFT    (0x00000018U)
71 #define BSP_RESET_MRCTL_BIT25_SHIFT    (0x00000019U)
72 #define BSP_RESET_MRCTL_BIT26_SHIFT    (0x0000001AU)
73 #define BSP_RESET_MRCTL_BIT27_SHIFT    (0x0000001BU)
74 #define BSP_RESET_MRCTL_BIT28_SHIFT    (0x0000001CU)
75 #define BSP_RESET_MRCTL_BIT29_SHIFT    (0x0000001DU)
76 #define BSP_RESET_MRCTL_BIT30_SHIFT    (0x0000001EU)
77 #define BSP_RESET_MRCTL_BIT31_SHIFT    (0x0000001FU)
78 
79 /***********************************************************************************************************************
80  * Typedef definitions
81  **********************************************************************************************************************/
82 
83 /*******************************************************************************************************************//**
84  * @addtogroup BSP_MCU
85  * @{
86  **********************************************************************************************************************/
87 
88 /** CPU to be reset target.*/
89 typedef enum e_bsp_reset
90 {
91     BSP_RESET_CR52_0 = 0,              ///< Software reset for CR52_0
92 } bsp_reset_t;
93 
94 /** The different types of registers that can control the reset of peripheral modules related to Ethernet. */
95 typedef enum e_bsp_module_reset
96 {
97     /** Enables writing to the registers related to xSPI Unit 0 reset control. */
98     BSP_MODULE_RESET_XSPI0 = (BSP_RESET_MRCTLA_SELECT | BSP_RESET_MRCTL_BIT4_SHIFT),
99 
100     /** Enables writing to the registers related to xSPI Unit 1 reset control. */
101     BSP_MODULE_RESET_XSPI1 = (BSP_RESET_MRCTLA_SELECT | BSP_RESET_MRCTL_BIT5_SHIFT),
102 
103     /** Enables writing to the registers related to GMAC (PCLKH clock domain) reset control. */
104     BSP_MODULE_RESET_GMAC0_PCLKH = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT0_SHIFT),
105 
106     /** Enables writing to the registers related to GMAC (PCLKM clock domain) reset control. */
107     BSP_MODULE_RESET_GMAC0_PCLKM = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT1_SHIFT),
108 
109     /** Enables writing to the registers related to ETHSW reset control. */
110     BSP_MODULE_RESET_ETHSW = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT2_SHIFT),
111 
112     /** Enables writing to the registers related to ESC (Bus clock domain) reset control. */
113     BSP_MODULE_RESET_ESC_BUS = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT3_SHIFT),
114 
115     /** Enables writing to the registers related to ESC (IP clock domain) reset control. */
116     BSP_MODULE_RESET_ESC_IP = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT4_SHIFT),
117 
118     /** Enables writing to the registers related to Ethernet subsystem register reset control. */
119     BSP_MODULE_RESET_ESC_ETH_SUBSYSTEM = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT5_SHIFT),
120 
121     /** Enables writing to the registers related to MII converter reset control. */
122     BSP_MODULE_RESET_MII = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT6_SHIFT),
123 
124     /** Enables writing to the registers related to PHOSTIF reset control. */
125     BSP_MODULE_RESET_PHOSTIF = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT0_SHIFT),
126 
127     /** Enables writing to the registers related to SHOSTIF (Master bus clock domain) reset control. */
128     BSP_MODULE_RESET_SHOSTIF_MASTER_BUS_CLOCK = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT1_SHIFT),
129 
130     /** Enables writing to the registers related to SHOSTIF (Slave bus clock domain) reset control. */
131     BSP_MODULE_RESET_SHOSTIF_SLAVE_BUS_CLOCK = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT2_SHIFT),
132 
133     /** Enables writing to the registers related to SHOSTIF (IP clock domain) reset control. */
134     BSP_MODULE_RESET_SHOSTIF_IP_CLOCK = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT3_SHIFT),
135 } bsp_module_reset_t;
136 
137 /** @} (end addtogroup BSP_MCU) */
138 
139 /***********************************************************************************************************************
140  * Exported global variables
141  **********************************************************************************************************************/
142 
143 /***********************************************************************************************************************
144  * Exported global functions (to be accessed by other files)
145  **********************************************************************************************************************/
146 
147 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
148 FSP_FOOTER
149 
150 #endif
151