1/* 2 Linker File for Renesas RZ/N2L FSP 3*/ 4/* The memory information for each device is done in memory regions file. 5 * The starting address and length of memory not defined in memory regions file are defined as 0. */ 6 7/* generated memory regions file - do not edit */ 8ATCM_START = 0x00000000; 9ATCM_LENGTH = 0x20000; 10BTCM_START = 0x00100000; 11BTCM_LENGTH = 0x20000; 12SYSTEM_RAM_START = 0x10000000; 13SYSTEM_RAM_LENGTH = 0x180000; 14SYSTEM_RAM_MIRROR_START = 0x30000000; 15SYSTEM_RAM_MIRROR_LENGTH = 0x180000; 16xSPI0_CS0_SPACE_MIRROR_START = 0x40000000; 17xSPI0_CS0_SPACE_MIRROR_LENGTH = 0x4000000; 18xSPI0_CS1_SPACE_MIRROR_START = 0x44000000; 19xSPI0_CS1_SPACE_MIRROR_LENGTH = 0x4000000; 20xSPI1_CS0_SPACE_MIRROR_START = 0x48000000; 21xSPI1_CS0_SPACE_MIRROR_LENGTH = 0x4000000; 22CS0_SPACE_MIRROR_START = 0x50000000; 23CS0_SPACE_MIRROR_LENGTH = 0x4000000; 24CS2_SPACE_MIRROR_START = 0x54000000; 25CS2_SPACE_MIRROR_LENGTH = 0x4000000; 26CS3_SPACE_MIRROR_START = 0x58000000; 27CS3_SPACE_MIRROR_LENGTH = 0x4000000; 28CS5_SPACE_MIRROR_START = 0x5C000000; 29CS5_SPACE_MIRROR_LENGTH = 0x4000000; 30xSPI0_CS0_SPACE_START = 0x60000000; 31xSPI0_CS0_SPACE_LENGTH = 0x4000000; 32xSPI0_CS1_SPACE_START = 0x64000000; 33xSPI0_CS1_SPACE_LENGTH = 0x4000000; 34xSPI1_CS0_SPACE_START = 0x68000000; 35xSPI1_CS0_SPACE_LENGTH = 0x4000000; 36CS0_SPACE_START = 0x70000000; 37CS0_SPACE_LENGTH = 0x4000000; 38CS2_SPACE_START = 0x74000000; 39CS2_SPACE_LENGTH = 0x4000000; 40CS3_SPACE_START = 0x78000000; 41CS3_SPACE_LENGTH = 0x4000000; 42CS5_SPACE_START = 0x7C000000; 43CS5_SPACE_LENGTH = 0x4000000; 44 45ATCM_PRV_START = DEFINED(ATCM_START) ? ATCM_START : 0; 46ATCM_PRV_LENGTH = DEFINED(ATCM_LENGTH) ? ATCM_LENGTH : 0; 47BTCM_PRV_START = DEFINED(BTCM_START) ? BTCM_START : 0; 48BTCM_PRV_LENGTH = DEFINED(BTCM_LENGTH) ? BTCM_LENGTH : 0; 49SYSTEM_RAM_PRV_START = DEFINED(SYSTEM_RAM_START) ? SYSTEM_RAM_START : 0; 50SYSTEM_RAM_PRV_LENGTH = DEFINED(SYSTEM_RAM_LENGTH) ? SYSTEM_RAM_LENGTH : 0; 51SYSTEM_RAM_MIRROR_PRV_START = DEFINED(SYSTEM_RAM_MIRROR_START) ? SYSTEM_RAM_MIRROR_START : 0; 52SYSTEM_RAM_MIRROR_PRV_LENGTH = DEFINED(SYSTEM_RAM_MIRROR_LENGTH) ? SYSTEM_RAM_MIRROR_LENGTH : 0; 53xSPI0_CS0_SPACE_MIRROR_PRV_START = DEFINED(xSPI0_CS0_SPACE_MIRROR_START) ? xSPI0_CS0_SPACE_MIRROR_START : 0; 54xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = DEFINED(xSPI0_CS0_SPACE_MIRROR_LENGTH) ? xSPI0_CS0_SPACE_MIRROR_LENGTH : 0; 55xSPI0_CS1_SPACE_MIRROR_PRV_START = DEFINED(xSPI0_CS1_SPACE_MIRROR_START) ? xSPI0_CS1_SPACE_MIRROR_START : 0; 56xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = DEFINED(xSPI0_CS1_SPACE_MIRROR_LENGTH) ? xSPI0_CS1_SPACE_MIRROR_LENGTH : 0; 57xSPI1_CS0_SPACE_MIRROR_PRV_START = DEFINED(xSPI1_CS0_SPACE_MIRROR_START) ? xSPI1_CS0_SPACE_MIRROR_START : 0; 58xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = DEFINED(xSPI1_CS0_SPACE_MIRROR_LENGTH) ? xSPI1_CS0_SPACE_MIRROR_LENGTH : 0; 59xSPI1_CS1_SPACE_MIRROR_PRV_START = DEFINED(xSPI1_CS1_SPACE_MIRROR_START) ? xSPI1_CS1_SPACE_MIRROR_START : 0; 60xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = DEFINED(xSPI1_CS1_SPACE_MIRROR_LENGTH) ? xSPI1_CS1_SPACE_MIRROR_LENGTH : 0; 61CS0_SPACE_MIRROR_PRV_START = DEFINED(CS0_SPACE_MIRROR_START) ? CS0_SPACE_MIRROR_START : 0; 62CS0_SPACE_MIRROR_PRV_LENGTH = DEFINED(CS0_SPACE_MIRROR_LENGTH) ? CS0_SPACE_MIRROR_LENGTH : 0; 63CS2_SPACE_MIRROR_PRV_START = DEFINED(CS2_SPACE_MIRROR_START) ? CS2_SPACE_MIRROR_START : 0; 64CS2_SPACE_MIRROR_PRV_LENGTH = DEFINED(CS2_SPACE_MIRROR_LENGTH) ? CS2_SPACE_MIRROR_LENGTH : 0; 65CS3_SPACE_MIRROR_PRV_START = DEFINED(CS3_SPACE_MIRROR_START) ? CS3_SPACE_MIRROR_START : 0; 66CS3_SPACE_MIRROR_PRV_LENGTH = DEFINED(CS3_SPACE_MIRROR_LENGTH) ? CS3_SPACE_MIRROR_LENGTH : 0; 67CS5_SPACE_MIRROR_PRV_START = DEFINED(CS5_SPACE_MIRROR_START) ? CS5_SPACE_MIRROR_START : 0; 68CS5_SPACE_MIRROR_PRV_LENGTH = DEFINED(CS5_SPACE_MIRROR_LENGTH) ? CS5_SPACE_MIRROR_LENGTH : 0; 69xSPI0_CS0_SPACE_PRV_START = DEFINED(xSPI0_CS0_SPACE_START) ? xSPI0_CS0_SPACE_START : 0; 70xSPI0_CS0_SPACE_PRV_LENGTH = DEFINED(xSPI0_CS0_SPACE_LENGTH) ? xSPI0_CS0_SPACE_LENGTH : 0; 71xSPI0_CS1_SPACE_PRV_START = DEFINED(xSPI0_CS1_SPACE_START) ? xSPI0_CS1_SPACE_START : 0; 72xSPI0_CS1_SPACE_PRV_LENGTH = DEFINED(xSPI0_CS1_SPACE_LENGTH) ? xSPI0_CS1_SPACE_LENGTH : 0; 73xSPI1_CS0_SPACE_PRV_START = DEFINED(xSPI1_CS0_SPACE_START) ? xSPI1_CS0_SPACE_START : 0; 74xSPI1_CS0_SPACE_PRV_LENGTH = DEFINED(xSPI1_CS0_SPACE_LENGTH) ? xSPI1_CS0_SPACE_LENGTH : 0; 75xSPI1_CS1_SPACE_PRV_START = DEFINED(xSPI1_CS1_SPACE_START) ? xSPI1_CS1_SPACE_START : 0; 76xSPI1_CS1_SPACE_PRV_LENGTH = DEFINED(xSPI1_CS1_SPACE_LENGTH) ? xSPI1_CS1_SPACE_LENGTH : 0; 77CS0_SPACE_PRV_START = DEFINED(CS0_SPACE_START) ? CS0_SPACE_START : 0; 78CS0_SPACE_PRV_LENGTH = DEFINED(CS0_SPACE_LENGTH) ? CS0_SPACE_LENGTH : 0; 79CS2_SPACE_PRV_START = DEFINED(CS2_SPACE_START) ? CS2_SPACE_START : 0; 80CS2_SPACE_PRV_LENGTH = DEFINED(CS2_SPACE_LENGTH) ? CS2_SPACE_LENGTH : 0; 81CS3_SPACE_PRV_START = DEFINED(CS3_SPACE_START) ? CS3_SPACE_START : 0; 82CS3_SPACE_PRV_LENGTH = DEFINED(CS3_SPACE_LENGTH) ? CS3_SPACE_LENGTH : 0; 83CS5_SPACE_PRV_START = DEFINED(CS5_SPACE_START) ? CS5_SPACE_START : 0; 84CS5_SPACE_PRV_LENGTH = DEFINED(CS5_SPACE_LENGTH) ? CS5_SPACE_LENGTH : 0; 85 86LOADER_PARAM_ADDRESS = xSPI0_CS0_SPACE_PRV_START; 87FLASH_CONTENTS_ADDRESS = LOADER_PARAM_ADDRESS + 0x0000004C; 88LOADER_TEXT_ADDRESS = 0x00102000; 89INTVEC_ADDRESS = 0x10000000; 90TEXT_ADDRESS = 0x10020000; 91NONCACHE_BUFFER_OFFSET = 0x00020000; 92DMAC_LINK_MODE_OFFSET = 0x00044000; 93DATA_NONCACHE_OFFSET = 0x00048000; 94RAM_START = SYSTEM_RAM_PRV_START; 95RAM_LENGTH = SYSTEM_RAM_PRV_LENGTH; 96LOADER_START = BTCM_PRV_START; 97LOADER_LENGTH = BTCM_PRV_LENGTH; 98 99/* Define starting addresses and length for data_noncache, DMAC link mode data, CPU-shared non-cache, and CPU-specific non-cache areas. */ 100DATA_NONCACHE_START = DEFINED(SYSTEM_RAM_MIRROR_START) ? SYSTEM_RAM_MIRROR_START + SYSTEM_RAM_MIRROR_LENGTH - DATA_NONCACHE_OFFSET : 0; 101DATA_NONCACHE_LENGTH = DEFINED(SYSTEM_RAM_MIRROR_LENGTH) ? 0x00004000 : 0; 102DMAC_LINK_MODE_START = DEFINED(SYSTEM_RAM_MIRROR_START) ? SYSTEM_RAM_MIRROR_START + SYSTEM_RAM_MIRROR_LENGTH - DMAC_LINK_MODE_OFFSET : 0; 103DMAC_LINK_MODE_LENGTH = DEFINED(SYSTEM_RAM_MIRROR_LENGTH) ? 0x00004000 : 0; 104SHARED_NONCACHE_BUFFER_START = DEFINED(SYSTEM_RAM_MIRROR_START) ? SYSTEM_RAM_MIRROR_START + SYSTEM_RAM_MIRROR_LENGTH - 0x00040000 : 0; 105SHARED_NONCACHE_BUFFER_LENGTH = DEFINED(SYSTEM_RAM_MIRROR_LENGTH) ? 0x00020000 : 0; 106NONCACHE_BUFFER_START = DEFINED(SYSTEM_RAM_MIRROR_START) ? SYSTEM_RAM_MIRROR_START + SYSTEM_RAM_MIRROR_LENGTH - NONCACHE_BUFFER_OFFSET : 0; 107NONCACHE_BUFFER_LENGTH = DEFINED(SYSTEM_RAM_MIRROR_LENGTH) ? 0x00020000 : 0; 108 109MEMORY 110{ 111 ATCM : ORIGIN = ATCM_PRV_START, LENGTH = ATCM_PRV_LENGTH 112 BTCM : ORIGIN = BTCM_PRV_START, LENGTH = BTCM_PRV_LENGTH 113 SYSTEM_RAM : ORIGIN = SYSTEM_RAM_PRV_START, LENGTH = SYSTEM_RAM_PRV_LENGTH 114 SYSTEM_RAM_MIRROR : ORIGIN = SYSTEM_RAM_MIRROR_PRV_START, LENGTH = SYSTEM_RAM_MIRROR_PRV_LENGTH 115 xSPI0_CS0_SPACE_MIRROR : ORIGIN = xSPI0_CS0_SPACE_MIRROR_PRV_START, LENGTH = xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH 116 xSPI0_CS1_SPACE_MIRROR : ORIGIN = xSPI0_CS1_SPACE_MIRROR_PRV_START, LENGTH = xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH 117 xSPI1_CS0_SPACE_MIRROR : ORIGIN = xSPI1_CS0_SPACE_MIRROR_PRV_START, LENGTH = xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH 118 xSPI1_CS1_SPACE_MIRROR : ORIGIN = xSPI1_CS1_SPACE_MIRROR_PRV_START, LENGTH = xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH 119 CS0_SPACE_MIRROR : ORIGIN = CS0_SPACE_MIRROR_PRV_START, LENGTH = CS0_SPACE_MIRROR_PRV_LENGTH 120 CS2_SPACE_MIRROR : ORIGIN = CS2_SPACE_MIRROR_PRV_START, LENGTH = CS2_SPACE_MIRROR_PRV_LENGTH 121 CS3_SPACE_MIRROR : ORIGIN = CS3_SPACE_MIRROR_PRV_START, LENGTH = CS3_SPACE_MIRROR_PRV_LENGTH 122 CS5_SPACE_MIRROR : ORIGIN = CS5_SPACE_MIRROR_PRV_START, LENGTH = CS5_SPACE_MIRROR_PRV_LENGTH 123 xSPI0_CS0_SPACE : ORIGIN = xSPI0_CS0_SPACE_PRV_START, LENGTH = xSPI0_CS0_SPACE_PRV_LENGTH 124 xSPI0_CS1_SPACE : ORIGIN = xSPI0_CS1_SPACE_PRV_START, LENGTH = xSPI0_CS1_SPACE_PRV_LENGTH 125 xSPI1_CS0_SPACE : ORIGIN = xSPI1_CS0_SPACE_PRV_START, LENGTH = xSPI1_CS0_SPACE_PRV_LENGTH 126 xSPI1_CS1_SPACE : ORIGIN = xSPI1_CS1_SPACE_PRV_START, LENGTH = xSPI1_CS1_SPACE_PRV_LENGTH 127 CS0_SPACE : ORIGIN = CS0_SPACE_PRV_START, LENGTH = CS0_SPACE_PRV_LENGTH 128 CS2_SPACE : ORIGIN = CS2_SPACE_PRV_START, LENGTH = CS2_SPACE_PRV_LENGTH 129 CS3_SPACE : ORIGIN = CS3_SPACE_PRV_START, LENGTH = CS3_SPACE_PRV_LENGTH 130 CS5_SPACE : ORIGIN = CS5_SPACE_PRV_START, LENGTH = CS5_SPACE_PRV_LENGTH 131 RAM : ORIGIN = RAM_START, LENGTH = RAM_LENGTH 132 LOADER_STACK : ORIGIN = LOADER_START, LENGTH = LOADER_LENGTH 133 DUMMY : ORIGIN = RAM_START, LENGTH = RAM_LENGTH 134 DATA_NONCACHE : ORIGIN = DATA_NONCACHE_START, LENGTH = DATA_NONCACHE_LENGTH 135 DMAC_LINK_MODE : ORIGIN = DMAC_LINK_MODE_START, LENGTH = DMAC_LINK_MODE_LENGTH 136 SHARED_NONCACHE_BUFFER : ORIGIN = SHARED_NONCACHE_BUFFER_START, LENGTH = SHARED_NONCACHE_BUFFER_LENGTH 137 NONCACHE_BUFFER : ORIGIN = NONCACHE_BUFFER_START, LENGTH = NONCACHE_BUFFER_LENGTH 138} 139 140SECTIONS 141{ 142 .loader_param LOADER_PARAM_ADDRESS : AT (LOADER_PARAM_ADDRESS) 143 { 144 KEEP(*(.loader_param)) 145 } > xSPI0_CS0_SPACE 146 .flash_contents FLASH_CONTENTS_ADDRESS : AT (FLASH_CONTENTS_ADDRESS) 147 { 148 _mloader_text = .; 149 . = . + (_loader_text_end - _loader_text_start); 150 _mloader_data = .; 151 . = . + (_loader_data_end - _loader_data_start); 152 _mfvector = .; 153 . = . + (_fvector_end - _fvector_start); 154 _mtext = .; 155 . = . + (_text_end - _text_start); 156 _mdummy = .; 157 . = . + (_dummy_end - _dummy_start); 158 _mdata = .; 159 . = . + (_data_end - _data_start); 160 _mdata_noncache = .; 161 . = . + (_data_noncache_end - _data_noncache_start); 162 flash_contents_end = .; 163 } > xSPI0_CS0_SPACE 164 .loader_text LOADER_TEXT_ADDRESS : AT (_mloader_text) 165 { 166 _loader_text_start = .; 167 *(.loader_text) 168 */fsp/src/bsp/cmsis/Device/RENESAS/Source/*.o(.text*) 169 */fsp/src/bsp/mcu/all/*/bsp_irq_core.o(.text*) 170 */fsp/src/bsp/mcu/all/bsp_clocks.o(.text*) 171 */fsp/src/bsp/mcu/all/bsp_irq.o(.text*) 172 */fsp/src/bsp/mcu/all/bsp_register_protection.o(.text*) 173 */fsp/src/bsp/mcu/all/bsp_cache.o(.text*) 174 */fsp/src/r_ioport/r_ioport.o(.text*) 175 KEEP(*(.warm_start)) 176 . = . + (512 - ((. - _loader_text_start) % 512)); 177 _loader_text_end = .; 178 } > LOADER_STACK 179 .loader_data : AT (_mloader_data) 180 { 181 _loader_data_start = .; 182 __loader_data_start = .; 183 */fsp/src/bsp/cmsis/Device/RENESAS/Source/*.o(.data*) 184 */fsp/src/bsp/cmsis/Device/RENESAS/Source/*/system_core.o(.rodata*) 185 */fsp/src/bsp/mcu/all/*/bsp_irq_core.o(.data*) 186 */fsp/src/bsp/mcu/all/bsp_clocks.o(.data*) 187 */fsp/src/bsp/mcu/all/bsp_irq.o(.data*) 188 */fsp/src/bsp/mcu/all/bsp_register_protection.o(.data*) 189 */fsp/src/bsp/mcu/all/bsp_cache.o(.data*) 190 */fsp/src/r_ioport/r_ioport.o(.data*) 191 . = ALIGN(4); 192 __loader_data_end = .; 193 __loader_bss_start = .; 194 */fsp/src/bsp/cmsis/Device/RENESAS/Source/*.o(.bss*) 195 */fsp/src/bsp/mcu/all/*/bsp_irq_core.o(.bss*) 196 */fsp/src/bsp/mcu/all/bsp_clocks.o(.bss*) 197 */fsp/src/bsp/mcu/all/bsp_irq.o(.bss*) 198 */fsp/src/bsp/mcu/all/bsp_register_protection.o(.bss*) 199 */fsp/src/bsp/mcu/all/bsp_cache.o(.bss*) 200 */fsp/src/r_ioport/r_ioport.o(.bss*) 201 */fsp/src/bsp/cmsis/Device/RENESAS/Source/*.o(COMMON) 202 */fsp/src/bsp/mcu/all/*/bsp_irq_core.o(COMMON) 203 */fsp/src/bsp/mcu/all/bsp_clocks.o(COMMON) 204 */fsp/src/bsp/mcu/all/bsp_irq.o(COMMON) 205 */fsp/src/bsp/mcu/all/bsp_register_protection.o(.COMMON) 206 */fsp/src/bsp/mcu/all/bsp_cache.o(COMMON) 207 */fsp/src/r_ioport/r_ioport.o(.COMMON) 208 . = ALIGN(4); 209 __loader_bss_end = . ; 210 _loader_data_end = .; 211 } > LOADER_STACK 212 .intvec INTVEC_ADDRESS : AT (_mfvector) 213 { 214 _fvector_start = .; 215 KEEP(*(.intvec)) 216 _fvector_end = .; 217 } > RAM 218 .text TEXT_ADDRESS : AT (_mtext) 219 { 220 _text_start = .; 221 *(.text*) 222 223 KEEP(*(.reset_handler)) 224 KEEP(*(.init)) 225 KEEP(*(.fini)) 226 227 /* .ctors */ 228 *crtbegin.o(.ctors) 229 *crtbegin?.o(.ctors) 230 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) 231 *(SORT(.ctors.*)) 232 *(.ctors) 233 _ctor_end = .; 234 235 /* .dtors */ 236 *crtbegin.o(.dtors) 237 *crtbegin?.o(.dtors) 238 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) 239 *(SORT(.dtors.*)) 240 *(.dtors) 241 _dtor_end = .; 242 243 /* section information for utest */ 244 . = ALIGN(4); 245 __rt_utest_tc_tab_start = .; 246 KEEP(*(UtestTcTab)) 247 __rt_utest_tc_tab_end = .; 248 249 /* section information for finsh shell */ 250 . = ALIGN(4); 251 __fsymtab_start = .; 252 KEEP(*(FSymTab)) 253 __fsymtab_end = .; 254 255 . = ALIGN(4); 256 __vsymtab_start = .; 257 KEEP(*(VSymTab)) 258 __vsymtab_end = .; 259 260 /* section information for initial. */ 261 . = ALIGN(4); 262 __rt_init_start = .; 263 KEEP(*(SORT(.rti_fn*))) 264 __rt_init_end = .; 265 266 /* new GCC version uses .init_array */ 267 PROVIDE(__ctors_start__ = .); 268 KEEP (*(SORT(.init_array.*))) 269 KEEP (*(.init_array)) 270 PROVIDE(__ctors_end__ = .); 271 272 . = ALIGN(4); 273 KEEP(*(FalPartTable)) 274 275 KEEP(*(.eh_frame*)) 276 } > RAM 277 .rvectors : 278 { 279 _rvectors_start = .; 280 KEEP(*(.rvectors)) 281 _rvectors_end = .; 282 } > RAM 283 .ARM.extab : 284 { 285 *(.ARM.extab* .gnu.linkonce.armextab.*) 286 } > RAM 287 __exidx_start = .; 288 .ARM.exidx : 289 { 290 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 291 } > RAM 292 __exidx_end = .; 293 .got : 294 { 295 *(.got) 296 *(.got.plt) 297 . = ALIGN(4); 298 _text_end = .; 299 } > RAM 300 .dummy _fvector_end : AT (_mdummy) 301 { 302 _dummy_start = .; 303 KEEP(*(.dummy)); 304 _dummy_end = .; 305 } > DUMMY 306 .data : AT (_mdata) 307 { 308 _data_start = .; 309 310 *(vtable) 311 *(.data.*) 312 *(.data) 313 314 *(.rodata*) 315 _erodata = .; 316 317 . = ALIGN(4); 318 /* preinit data */ 319 PROVIDE_HIDDEN (__preinit_array_start = .); 320 KEEP(*(.preinit_array)) 321 PROVIDE_HIDDEN (__preinit_array_end = .); 322 323 . = ALIGN(4); 324 /* init data */ 325 PROVIDE_HIDDEN (__init_array_start = .); 326 KEEP(*(SORT(.init_array.*))) 327 KEEP(*(.init_array)) 328 PROVIDE_HIDDEN (__init_array_end = .); 329 330 . = ALIGN(4); 331 /* finit data */ 332 PROVIDE_HIDDEN (__fini_array_start = .); 333 KEEP(*(SORT(.fini_array.*))) 334 KEEP(*(.fini_array)) 335 PROVIDE_HIDDEN (__fini_array_end = .); 336 337 KEEP(*(.jcr*)) 338 339 . = ALIGN(4); 340 341 /* All data end */ 342 _data_end = .; 343 } > RAM 344 .bss : 345 { 346 . = ALIGN(4); 347 __bss_start__ = .; 348 _bss = .; 349 *(.bss*) 350 *(COMMON) 351 . = ALIGN(4); 352 __bss_end__ = .; 353 _ebss = .; 354 _end = .; 355 } > RAM 356 .heap (NOLOAD) : 357 { 358 . = ALIGN(8); 359 __HeapBase = .; 360 /* Place the STD heap here. */ 361 KEEP(*(.heap)) 362 __HeapLimit = .; 363 } > RAM 364 .thread_stack (NOLOAD): 365 { 366 . = ALIGN(8); 367 __ThreadStackBase = .; 368 /* Place the Thread stacks here. */ 369 KEEP(*(.stack*)) 370 __ThreadStackLimit = .; 371 } > RAM 372 .sys_stack (NOLOAD) : 373 { 374 . = ALIGN(8); 375 __SysStackBase = .; 376 /* Place the sys_stack here. */ 377 KEEP(*(.sys_stack)) 378 __SysStackLimit = .; 379 } > LOADER_STACK 380 .svc_stack (NOLOAD) : 381 { 382 . = ALIGN(8); 383 __SvcStackBase = .; 384 /* Place the svc_stack here. */ 385 KEEP(*(.svc_stack)) 386 __SvcStackLimit = .; 387 } > LOADER_STACK 388 .irq_stack (NOLOAD) : 389 { 390 . = ALIGN(8); 391 __IrqStackBase = .; 392 /* Place the irq_stack here. */ 393 KEEP(*(.irq_stack)) 394 __IrqStackLimit = .; 395 } > LOADER_STACK 396 .fiq_stack (NOLOAD) : 397 { 398 . = ALIGN(8); 399 __FiqStackBase = .; 400 /* Place the fiq_stack here. */ 401 KEEP(*(.fiq_stack)) 402 __FiqStackLimit = .; 403 } > LOADER_STACK 404 .und_stack (NOLOAD) : 405 { 406 . = ALIGN(8); 407 __UndStackBase = .; 408 /* Place the und_stack here. */ 409 KEEP(*(.und_stack)) 410 __UndStackLimit = .; 411 } > LOADER_STACK 412 .abt_stack (NOLOAD) : 413 { 414 . = ALIGN(8); 415 __AbtStackBase = .; 416 /* Place the abt_stack here. */ 417 KEEP(*(.abt_stack)) 418 __AbtStackLimit = .; 419 } > LOADER_STACK 420 .data_noncache DATA_NONCACHE_START : AT (_mdata_noncache) 421 { 422 . = ALIGN(4); 423 _data_noncache_start = .; 424 KEEP(*(.data_noncache*)) 425 _data_noncache_end = .; 426 } > DATA_NONCACHE 427 .dmac_link_mode DMAC_LINK_MODE_START : AT (DMAC_LINK_MODE_START) 428 { 429 . = ALIGN(4); 430 _DmacLinkMode_start = .; 431 KEEP(*(.dmac_link_mode*)) 432 _DmacLinkMode_end = .; 433 } > DMAC_LINK_MODE 434 .shared_noncache_buffer SHARED_NONCACHE_BUFFER_START (NOLOAD) : AT (SHARED_NONCACHE_BUFFER_START) 435 { 436 . = ALIGN(32); 437 _sncbuffer_start = .; 438 KEEP(*(.shared_noncache_buffer*)) 439 _sncbuffer_end = .; 440 } > SHARED_NONCACHE_BUFFER 441 .noncache_buffer NONCACHE_BUFFER_START (NOLOAD) : AT (NONCACHE_BUFFER_START) 442 { 443 . = ALIGN(32); 444 _ncbuffer_start = .; 445 KEEP(*(.noncache_buffer*)) 446 _ncbuffer_end = .; 447 } > NONCACHE_BUFFER 448} 449