1 /*********************************************************************************************************************** 2 * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. 3 * 4 * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only 5 * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. 6 * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for 7 * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any 8 * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including 9 * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. 10 * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND 11 * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, 12 * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE 13 * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. 14 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR 15 * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, 16 * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY 17 * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE 18 * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. 19 **********************************************************************************************************************/ 20 21 #ifndef R_SCI_UART_H 22 #define R_SCI_UART_H 23 24 /*******************************************************************************************************************//** 25 * @addtogroup SCI_UART 26 * @{ 27 **********************************************************************************************************************/ 28 29 /*********************************************************************************************************************** 30 * Includes 31 **********************************************************************************************************************/ 32 #include "bsp_api.h" 33 #include "r_uart_api.h" 34 #include "r_sci_uart_cfg.h" 35 36 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 37 FSP_HEADER 38 39 /*********************************************************************************************************************** 40 * Macro definitions 41 **********************************************************************************************************************/ 42 43 /********************************************************************************************************************** 44 * Typedef definitions 45 **********************************************************************************************************************/ 46 47 /** Enumeration for SCI clock source */ 48 typedef enum e_sci_uart_clock 49 { 50 SCI_UART_CLOCK_INT, ///< Use internal clock for baud generation 51 SCI_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, ///< Use internal clock for baud generation and output on SCK 52 SCI_UART_CLOCK_EXT8X, ///< Use external clock 8x baud rate 53 SCI_UART_CLOCK_EXT16X ///< Use external clock 16x baud rate 54 } sci_uart_clock_t; 55 56 /** UART flow control mode definition */ 57 typedef enum e_sci_uart_flow_control 58 { 59 SCI_UART_FLOW_CONTROL_RTS = 0U, ///< Use CTSn_RTSn pin for RTS 60 SCI_UART_FLOW_CONTROL_CTS = 1U, ///< Use CTSn_RTSn pin for CTS 61 SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS = 3U, ///< Use CTSn pin for CTS, CTSn_RTSn pin for RTS 62 SCI_UART_FLOW_CONTROL_CTSRTS = 5U, ///< Use SCI pin for CTS, external pin for RTS 63 } sci_uart_flow_control_t; 64 65 /** UART instance control block. */ 66 typedef struct st_sci_uart_instance_ctrl 67 { 68 /* Parameters to control UART peripheral device */ 69 uint8_t fifo_depth; // FIFO depth of the UART channel 70 uint8_t rx_transfer_in_progress; // Set to 1 if a receive transfer is in progress, 0 otherwise 71 uint8_t data_bytes : 2; // 1 byte for 7 or 8 bit data, 2 bytes for 9 bit data 72 uint8_t bitrate_modulation : 1; // 1 if bit rate modulation is enabled, 0 otherwise 73 uint32_t open; // Used to determine if the channel is configured 74 75 bsp_io_port_pin_t flow_pin; 76 77 /* Source buffer pointer used to fill hardware FIFO from transmit ISR. */ 78 uint8_t const * p_tx_src; 79 80 /* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */ 81 uint32_t tx_src_bytes; 82 83 /* Destination buffer pointer used for receiving data. */ 84 uint8_t const * p_rx_dest; 85 86 /* Size of destination buffer pointer used for receiving data. */ 87 uint32_t rx_dest_bytes; 88 89 /* Pointer to the configuration block. */ 90 uart_cfg_t const * p_cfg; 91 92 /* Base register for this channel */ 93 R_SCI0_Type * p_reg; 94 95 void (* p_callback)(uart_callback_args_t *); // Pointer to callback that is called when a uart_event_t occurs. 96 uart_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. 97 98 /* Pointer to context to be passed into callback function */ 99 void const * p_context; 100 } sci_uart_instance_ctrl_t; 101 102 /** Receive FIFO trigger configuration. */ 103 typedef enum e_sci_uart_rx_fifo_trigger 104 { 105 SCI_UART_RX_FIFO_TRIGGER_1 = 0x1, ///< Callback after each byte is received without buffering 106 SCI_UART_RX_FIFO_TRIGGER_MAX = 0xF, ///< Callback when FIFO is full or after 15 bit times with no data (fewer interrupts) 107 } sci_uart_rx_fifo_trigger_t; 108 109 /** Asynchronous Start Bit Edge Detection configuration. */ 110 typedef enum e_sci_uart_start_bit 111 { 112 SCI_UART_START_BIT_LOW_LEVEL = 0x0, ///< Detect low level on RXDn pin as start bit 113 SCI_UART_START_BIT_FALLING_EDGE = 0x1, ///< Detect falling level on RXDn pin as start bit 114 } sci_uart_start_bit_t; 115 116 /** Noise cancellation configuration. */ 117 typedef enum e_sci_uart_noise_cancellation 118 { 119 SCI_UART_NOISE_CANCELLATION_DISABLE = 0x0, ///< Disable noise cancellation 120 SCI_UART_NOISE_CANCELLATION_ENABLE = 0x1, ///< Enable noise cancellation, The base clock signal divided by 1 121 SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_1 = 0x2, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 1 122 SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_2 = 0x3, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 2 123 SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_4 = 0x4, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 4 124 SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_8 = 0x5, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 8 125 } sci_uart_noise_cancellation_t; 126 127 /** RS-485 Enable/Disable. */ 128 typedef enum e_sci_uart_rs485_enable 129 { 130 SCI_UART_RS485_DISABLE = 0, ///< RS-485 disabled. 131 SCI_UART_RS485_ENABLE = 1, ///< RS-485 enabled. 132 } sci_uart_rs485_enable_t; 133 134 /** The polarity of the RS-485 DE signal. */ 135 typedef enum e_sci_uart_rs485_de_polarity 136 { 137 SCI_UART_RS485_DE_POLARITY_HIGH = 0, ///< The DE signal is high when a write transfer is in progress. 138 SCI_UART_RS485_DE_POLARITY_LOW = 1, ///< The DE signal is low when a write transfer is in progress. 139 } sci_uart_rs485_de_polarity_t; 140 141 /** Source clock selection options for SCI. */ 142 typedef enum e_sci_uart_clock_source 143 { 144 SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK = 0, 145 SCI_UART_CLOCK_SOURCE_SCI1ASYNCCLK = 1, 146 SCI_UART_CLOCK_SOURCE_SCI2ASYNCCLK = 2, 147 SCI_UART_CLOCK_SOURCE_SCI3ASYNCCLK = 3, 148 SCI_UART_CLOCK_SOURCE_SCI4ASYNCCLK = 4, 149 SCI_UART_CLOCK_SOURCE_SCI5ASYNCCLK = 5, 150 SCI_UART_CLOCK_SOURCE_PCLKM = 6, 151 } sci_uart_clock_source_t; 152 153 /** Baudrate calculation configuration. */ 154 typedef struct st_sci_uart_baud_calculation 155 { 156 uint32_t baudrate; ///< Target baudrate 157 bool bitrate_modulation; ///< Whether bitrate modulation use or not 158 uint32_t baud_rate_error_x_1000; ///< Max baudrate percent error 159 } sci_uart_baud_calculation_t; 160 161 /** Register settings to achieve a desired baud rate and modulation duty. */ 162 typedef struct st_sci_baud_setting_t 163 { 164 union 165 { 166 uint32_t baudrate_bits; 167 168 struct 169 { 170 uint32_t : 4; 171 uint32_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select 172 uint32_t abcs : 1; ///< Asynchronous Mode Base Clock Select 173 uint32_t abcse : 1; ///< Asynchronous Mode Extended Base Clock Select 1 174 uint32_t : 1; 175 uint32_t brr : 8; ///< Bit Rate Register setting 176 uint32_t brme : 1; ///< Bit Rate Modulation Enable 177 uint32_t : 3; 178 uint32_t cks : 2; ///< CKS value to get divisor (CKS = N) 179 uint32_t : 2; 180 uint32_t mddr : 8; ///< Modulation Duty Register setting 181 } baudrate_bits_b; 182 }; 183 } sci_baud_setting_t; 184 185 /** Configuration settings for controlling the DE signal for RS-485. */ 186 typedef struct st_sci_uart_rs485_setting 187 { 188 sci_uart_rs485_enable_t enable; ///< Enable the DE signal. 189 sci_uart_rs485_de_polarity_t polarity; ///< DE signal polarity. 190 uint8_t assertion_time : 5; ///< Time in baseclock units after assertion of the DE signal and before the start of the write transfer. 191 uint8_t negation_time : 5; ///< Time in baseclock units after the end of a write transfer and before the DE signal is negated. 192 } sci_uart_rs485_setting_t; 193 194 /** UART on SCI device Configuration */ 195 typedef struct st_sci_uart_extended_cfg 196 { 197 sci_uart_clock_t clock; ///< The source clock for the baud-rate generator. If internal optionally output baud rate on SCK 198 sci_uart_start_bit_t rx_edge_start; ///< Start reception on falling edge 199 sci_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting 200 201 sci_baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate. 202 203 sci_uart_rx_fifo_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level, unused if channel has no FIFO or if DMAC is used. 204 205 bsp_io_port_pin_t flow_control_pin; ///< UART Driver Enable pin 206 sci_uart_flow_control_t flow_control; ///< CTS/RTS function 207 sci_uart_rs485_setting_t rs485_setting; ///< RS-485 settings. 208 209 /** Clock source to generate SCK can either be selected as PCLKM or SCInASYNCCLK. */ 210 sci_uart_clock_source_t clock_source; 211 } sci_uart_extended_cfg_t; 212 213 /********************************************************************************************************************** 214 * Exported global variables 215 **********************************************************************************************************************/ 216 217 /** @cond INC_HEADER_DEFS_SEC */ 218 /** Filled in Interface API structure for this Instance. */ 219 extern const uart_api_t g_uart_on_sci; 220 221 /** @endcond */ 222 223 fsp_err_t R_SCI_UART_Open(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); 224 fsp_err_t R_SCI_UART_Read(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes); 225 fsp_err_t R_SCI_UART_Write(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes); 226 fsp_err_t R_SCI_UART_BaudSet(uart_ctrl_t * const p_ctrl, void const * const p_baud_setting); 227 fsp_err_t R_SCI_UART_InfoGet(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info); 228 fsp_err_t R_SCI_UART_Close(uart_ctrl_t * const p_ctrl); 229 fsp_err_t R_SCI_UART_Abort(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort); 230 fsp_err_t R_SCI_UART_BaudCalculate(sci_uart_baud_calculation_t const * const p_baud_target, 231 sci_uart_clock_source_t clock_source, 232 sci_baud_setting_t * const p_baud_setting); 233 fsp_err_t R_SCI_UART_CallbackSet(uart_ctrl_t * const p_ctrl, 234 void ( * p_callback)(uart_callback_args_t *), 235 void const * const p_context, 236 uart_callback_args_t * const p_callback_memory); 237 fsp_err_t R_SCI_UART_ReadStop(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes); 238 239 /*******************************************************************************************************************//** 240 * @} (end addtogroup SCI_UART) 241 **********************************************************************************************************************/ 242 243 /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 244 FSP_FOOTER 245 246 #endif 247