1 /** @file reg_adc.h 2 * @brief ADC Register Layer Header File 3 * @date 29.May.2013 4 * @version 03.05.02 5 * 6 * This file contains: 7 * - Definitions 8 * - Types 9 * - Interface Prototypes 10 * . 11 * which are relevant for the ADC driver. 12 */ 13 14 /* (c) Texas Instruments 2009-2013, All rights reserved. */ 15 16 #ifndef __REG_ADC_H__ 17 #define __REG_ADC_H__ 18 19 #include "sys_common.h" 20 21 22 23 /* USER CODE BEGIN (0) */ 24 /* USER CODE END */ 25 26 /* Adc Register Frame Definition */ 27 /** @struct adcBase 28 * @brief ADC Register Frame Definition 29 * 30 * This type is used to access the ADC Registers. 31 */ 32 /** @typedef adcBASE_t 33 * @brief ADC Register Frame Type Definition 34 * 35 * This type is used to access the ADC Registers. 36 */ 37 typedef volatile struct adcBase 38 { 39 uint32 RSTCR; /**< 0x0000: Reset control register */ 40 uint32 OPMODECR; /**< 0x0004: Operating mode control register */ 41 uint32 CLOCKCR; /**< 0x0008: Clock control register */ 42 uint32 CALCR; /**< 0x000C: Calibration control register */ 43 uint32 GxMODECR[3U]; /**< 0x0010,0x0014,0x0018: Group 0-2 mode control register */ 44 uint32 G0SRC; /**< 0x001C: Group 0 trigger source control register */ 45 uint32 G1SRC; /**< 0x0020: Group 1 trigger source control register */ 46 uint32 G2SRC; /**< 0x0024: Group 2 trigger source control register */ 47 uint32 GxINTENA[3U]; /**< 0x0028,0x002C,0x0030: Group 0-2 interrupt enable register */ 48 uint32 GxINTFLG[3U]; /**< 0x0034,0x0038,0x003C: Group 0-2 interrupt flag register */ 49 uint32 GxINTCR[3U]; /**< 0x0040-0x0048: Group 0-2 interrupt threshold register */ 50 uint32 G0DMACR; /**< 0x004C: Group 0 DMA control register */ 51 uint32 G1DMACR; /**< 0x0050: Group 1 DMA control register */ 52 uint32 G2DMACR; /**< 0x0054: Group 2 DMA control register */ 53 uint32 BNDCR; /**< 0x0058: Buffer boundary control register */ 54 uint32 BNDEND; /**< 0x005C: Buffer boundary end register */ 55 uint32 G0SAMP; /**< 0x0060: Group 0 sample window register */ 56 uint32 G1SAMP; /**< 0x0064: Group 1 sample window register */ 57 uint32 G2SAMP; /**< 0x0068: Group 2 sample window register */ 58 uint32 G0SR; /**< 0x006C: Group 0 status register */ 59 uint32 G1SR; /**< 0x0070: Group 1 status register */ 60 uint32 G2SR; /**< 0x0074: Group 2 status register */ 61 uint32 GxSEL[3U]; /**< 0x0078-0x007C: Group 0-2 channel select register */ 62 uint32 CALR; /**< 0x0084: Calibration register */ 63 uint32 SMSTATE; /**< 0x0088: State machine state register */ 64 uint32 LASTCONV; /**< 0x008C: Last conversion register */ 65 struct 66 { 67 uint32 BUF0; /**< 0x0090,0x00B0,0x00D0: Group 0-2 result buffer 1 register */ 68 uint32 BUF1; /**< 0x0094,0x00B4,0x00D4: Group 0-2 result buffer 1 register */ 69 uint32 BUF2; /**< 0x0098,0x00B8,0x00D8: Group 0-2 result buffer 2 register */ 70 uint32 BUF3; /**< 0x009C,0x00BC,0x00DC: Group 0-2 result buffer 3 register */ 71 uint32 BUF4; /**< 0x00A0,0x00C0,0x00E0: Group 0-2 result buffer 4 register */ 72 uint32 BUF5; /**< 0x00A4,0x00C4,0x00E4: Group 0-2 result buffer 5 register */ 73 uint32 BUF6; /**< 0x00A8,0x00C8,0x00E8: Group 0-2 result buffer 6 register */ 74 uint32 BUF7; /**< 0x00AC,0x00CC,0x00EC: Group 0-2 result buffer 7 register */ 75 } GxBUF[3U]; 76 uint32 G0EMUBUFFER; /**< 0x00F0: Group 0 emulation result buffer */ 77 uint32 G1EMUBUFFER; /**< 0x00F4: Group 1 emulation result buffer */ 78 uint32 G2EMUBUFFER; /**< 0x00F8: Group 2 emulation result buffer */ 79 uint32 EVTDIR; /**< 0x00FC: Event pin direction register */ 80 uint32 EVTOUT; /**< 0x0100: Event pin digital output register */ 81 uint32 EVTIN; /**< 0x0104: Event pin digital input register */ 82 uint32 EVTSET; /**< 0x0108: Event pin set register */ 83 uint32 EVTCLR; /**< 0x010C: Event pin clear register */ 84 uint32 EVTPDR; /**< 0x0110: Event pin open drain register */ 85 uint32 EVTDIS; /**< 0x0114: Event pin pull disable register */ 86 uint32 EVTPSEL; /**< 0x0118: Event pin pull select register */ 87 uint32 G0SAMPDISEN; /**< 0x011C: Group 0 sample discharge register */ 88 uint32 G1SAMPDISEN; /**< 0x0120: Group 1 sample discharge register */ 89 uint32 G2SAMPDISEN; /**< 0x0124: Group 2 sample discharge register */ 90 uint32 MAGINTCR1; /**< 0x0128: Magnitude interrupt control register 1 */ 91 uint32 MAGINT1MASK; /**< 0x012C: Magnitude interrupt mask register 1 */ 92 uint32 MAGINTCR2; /**< 0x0130: Magnitude interrupt control register 2 */ 93 uint32 MAGINT2MASK; /**< 0x0134: Magnitude interrupt mask register 2 */ 94 uint32 MAGINTCR3; /**< 0x0138: Magnitude interrupt control register 3 */ 95 uint32 MAGINT3MASK; /**< 0x013C: Magnitude interrupt mask register 3 */ 96 uint32 MAGINTCR4; /**< 0x0140: Magnitude interrupt control register 4 */ 97 uint32 MAGINT4MASK; /**< 0x0144: Magnitude interrupt mask register 4 */ 98 uint32 MAGINTCR5; /**< 0x0148: Magnitude interrupt control register 5 */ 99 uint32 MAGINT5MASK; /**< 0x014C: Magnitude interrupt mask register 5 */ 100 uint32 MAGINTCR6; /**< 0x0150: Magnitude interrupt control register 6 */ 101 uint32 MAGINT6MASK; /**< 0x0154: Magnitude interrupt mask register 6 */ 102 uint32 MAGTHRINTENASET; /**< 0x0158: Magnitude interrupt set register */ 103 uint32 MAGTHRINTENACLR; /**< 0x015C: Magnitude interrupt clear register */ 104 uint32 MAGTHRINTFLG; /**< 0x0160: Magnitude interrupt flag register */ 105 uint32 MAGTHRINTOFFSET; /**< 0x0164: Magnitude interrupt offset register */ 106 uint32 GxFIFORESETCR[3U]; /**< 0x0168,0x016C,0x0170: Group 0-2 fifo reset register */ 107 uint32 G0RAMADDR; /**< 0x0174: Group 0 RAM pointer register */ 108 uint32 G1RAMADDR; /**< 0x0178: Group 1 RAM pointer register */ 109 uint32 G2RAMADDR; /**< 0x017C: Group 2 RAM pointer register */ 110 uint32 PARCR; /**< 0x0180: Parity control register */ 111 uint32 PARADDR; /**< 0x0184: Parity error address register */ 112 uint32 PWRUPDLYCTRL; /**< 0x0188: Power-Up delay control register */ 113 } adcBASE_t; 114 115 116 /** @def adcREG1 117 * @brief ADC1 Register Frame Pointer 118 * 119 * This pointer is used by the ADC driver to access the ADC1 registers. 120 */ 121 #define adcREG1 ((adcBASE_t *)0xFFF7C000U) 122 123 /** @def adcREG2 124 * @brief ADC2 Register Frame Pointer 125 * 126 * This pointer is used by the ADC driver to access the ADC2 registers. 127 */ 128 #define adcREG2 ((adcBASE_t *)0xFFF7C200U) 129 130 /** @def adcRAM1 131 * @brief ADC1 RAM Pointer 132 * 133 * This pointer is used by the ADC driver to access the ADC1 RAM. 134 */ 135 #define adcRAM1 (*(volatile uint32 *)0xFF3E0000U) 136 137 /** @def adcRAM2 138 * @brief ADC2 RAM Pointer 139 * 140 * This pointer is used by the ADC driver to access the ADC2 RAM. 141 */ 142 #define adcRAM2 (*(volatile uint32 *)0xFF3A0000U) 143 144 /** @def adcPARRAM1 145 * @brief ADC1 Parity RAM Pointer 146 * 147 * This pointer is used by the ADC driver to access the ADC1 Parity RAM. 148 */ 149 #define adcPARRAM1 (*(volatile uint32 *)(0xFF3E0000U + 0x1000U)) 150 151 /** @def adcPARRAM2 152 * @brief ADC2 Parity RAM Pointer 153 * 154 * This pointer is used by the ADC driver to access the ADC2 Parity RAM. 155 */ 156 #define adcPARRAM2 (*(volatile uint32 *)(0xFF3A0000U + 0x1000U)) 157 158 /* USER CODE BEGIN (1) */ 159 /* USER CODE END */ 160 161 162 #endif 163