1 /** @file reg_can.h 2 * @brief CAN Register Layer Header File 3 * @date 29.May.2013 4 * @version 03.05.02 5 * 6 * This file contains: 7 * - Definitions 8 * - Types 9 * - Interface Prototypes 10 * . 11 * which are relevant for the CAN driver. 12 */ 13 14 /* (c) Texas Instruments 2009-2013, All rights reserved. */ 15 16 #ifndef __REG_CAN_H__ 17 #define __REG_CAN_H__ 18 19 #include "sys_common.h" 20 21 22 23 /* USER CODE BEGIN (0) */ 24 /* USER CODE END */ 25 26 /* Can Register Frame Definition */ 27 /** @struct canBase 28 * @brief CAN Register Frame Definition 29 * 30 * This type is used to access the CAN Registers. 31 */ 32 /** @typedef canBASE_t 33 * @brief CAN Register Frame Type Definition 34 * 35 * This type is used to access the CAN Registers. 36 */ 37 typedef volatile struct canBase 38 { 39 uint32 CTL; /**< 0x0000: Control Register */ 40 uint32 ES; /**< 0x0004: Error and Status Register */ 41 uint32 EERC; /**< 0x0008: Error Counter Register */ 42 uint32 BTR; /**< 0x000C: Bit Timing Register */ 43 uint32 INT; /**< 0x0010: Interrupt Register */ 44 uint32 TEST; /**< 0x0014: Test Register */ 45 uint32 rsvd1; /**< 0x0018: Reserved */ 46 uint32 PERR; /**< 0x001C: Parity/SECDED Error Code Register */ 47 uint32 REL; /**< 0x0020: Core Release Register */ 48 uint32 ECCDIAG; /**< 0x0024: ECC Diagnostic Register */ 49 uint32 ECCDIADSTAT; /**< 0x0028: ECC Diagnostic Status Register */ 50 uint32 rsvd2[21]; /**< 0x002C: Reserved */ 51 uint32 ABOTR; /**< 0x0080: Auto Bus On Time Register */ 52 uint32 TXRQX; /**< 0x0084: Transmission Request X Register */ 53 uint32 TXRQx[4U]; /**< 0x0088-0x0094: Transmission Request Registers */ 54 uint32 NWDATX; /**< 0x0098: New Data X Register */ 55 uint32 NWDATx[4U]; /**< 0x009C-0x00A8: New Data Registers */ 56 uint32 INTPNDX; /**< 0x00AC: Interrupt Pending X Register */ 57 uint32 INTPNDx[4U]; /**< 0x00B0-0x00BC: Interrupt Pending Registers */ 58 uint32 MSGVALX; /**< 0x00C0: Message Valid X Register */ 59 uint32 MSGVALx[4U]; /**< 0x00C4-0x00D0: Message Valid Registers */ 60 uint32 rsvd3; /**< 0x00D4: Reserved */ 61 uint32 INTMUXx[4U]; /**< 0x00D8-0x00E4: Interrupt Multiplexer Registers */ 62 uint32 rsvd4[6]; /**< 0x00E8: Reserved */ 63 #if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1)) 64 uint8 IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */ 65 uint8 IF1STAT; /**< 0x0100: IF1 Command Register, Status */ 66 uint8 IF1CMD; /**< 0x0100: IF1 Command Register, Command */ 67 uint8 rsvd9; /**< 0x0100: IF1 Command Register, Reserved */ 68 #else 69 uint8 rsvd9; /**< 0x0100: IF1 Command Register, Reserved */ 70 uint8 IF1CMD; /**< 0x0100: IF1 Command Register, Command */ 71 uint8 IF1STAT; /**< 0x0100: IF1 Command Register, Status */ 72 uint8 IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */ 73 #endif 74 uint32 IF1MSK; /**< 0x0104: IF1 Mask Register */ 75 uint32 IF1ARB; /**< 0x0108: IF1 Arbitration Register */ 76 uint32 IF1MCTL; /**< 0x010C: IF1 Message Control Register */ 77 uint8 IF1DATx[8U]; /**< 0x0110-0x0114: IF1 Data A and B Registers */ 78 uint32 rsvd5[2]; /**< 0x0118: Reserved */ 79 #if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1)) 80 uint8 IF2NO; /**< 0x0120: IF2 Command Register, Msg No */ 81 uint8 IF2STAT; /**< 0x0120: IF2 Command Register, Status */ 82 uint8 IF2CMD; /**< 0x0120: IF2 Command Register, Command */ 83 uint8 rsvd10; /**< 0x0120: IF2 Command Register, Reserved */ 84 #else 85 uint8 rsvd10; /**< 0x0120: IF2 Command Register, Reserved */ 86 uint8 IF2CMD; /**< 0x0120: IF2 Command Register, Command */ 87 uint8 IF2STAT; /**< 0x0120: IF2 Command Register, Status */ 88 uint8 IF2NO; /**< 0x0120: IF2 Command Register, Msg Number */ 89 #endif 90 uint32 IF2MSK; /**< 0x0124: IF2 Mask Register */ 91 uint32 IF2ARB; /**< 0x0128: IF2 Arbitration Register */ 92 uint32 IF2MCTL; /**< 0x012C: IF2 Message Control Register */ 93 uint8 IF2DATx[8U]; /**< 0x0130-0x0134: IF2 Data A and B Registers */ 94 uint32 rsvd6[2]; /**< 0x0138: Reserved */ 95 uint32 IF3OBS; /**< 0x0140: IF3 Observation Register */ 96 uint32 IF3MSK; /**< 0x0144: IF3 Mask Register */ 97 uint32 IF3ARB; /**< 0x0148: IF3 Arbitration Register */ 98 uint32 IF3MCTL; /**< 0x014C: IF3 Message Control Register */ 99 uint8 IF3DATx[8U]; /**< 0x0150-0x0154: IF3 Data A and B Registers */ 100 uint32 rsvd7[2]; /**< 0x0158: Reserved */ 101 uint32 IF3UEy[4U]; /**< 0x0160-0x016C: IF3 Update Enable Registers */ 102 uint32 rsvd8[28]; /**< 0x0170: Reserved */ 103 uint32 TIOC; /**< 0x01E0: TX IO Control Register */ 104 uint32 RIOC; /**< 0x01E4: RX IO Control Register */ 105 } canBASE_t; 106 107 108 /** @def canREG1 109 * @brief CAN1 Register Frame Pointer 110 * 111 * This pointer is used by the CAN driver to access the CAN1 registers. 112 */ 113 #define canREG1 ((canBASE_t *)0xFFF7DC00U) 114 115 /** @def canREG2 116 * @brief CAN2 Register Frame Pointer 117 * 118 * This pointer is used by the CAN driver to access the CAN2 registers. 119 */ 120 #define canREG2 ((canBASE_t *)0xFFF7DE00U) 121 122 /** @def canREG3 123 * @brief CAN3 Register Frame Pointer 124 * 125 * This pointer is used by the CAN driver to access the CAN3 registers. 126 */ 127 #define canREG3 ((canBASE_t *)0xFFF7E000U) 128 129 /** @def canRAM1 130 * @brief CAN1 Mailbox RAM Pointer 131 * 132 * This pointer is used by the CAN driver to access the CAN1 RAM. 133 */ 134 #define canRAM1 (*(volatile uint32 *)0xFF1E0000U) 135 136 /** @def canRAM2 137 * @brief CAN2 Mailbox RAM Pointer 138 * 139 * This pointer is used by the CAN driver to access the CAN2 RAM. 140 */ 141 #define canRAM2 (*(volatile uint32 *)0xFF1C0000U) 142 143 /** @def canRAM3 144 * @brief CAN3 Mailbox RAM Pointer 145 * 146 * This pointer is used by the CAN driver to access the CAN3 RAM. 147 */ 148 #define canRAM3 (*(volatile uint32 *)0xFF1A0000U) 149 150 /** @def canPARRAM1 151 * @brief CAN1 Mailbox Parity RAM Pointer 152 * 153 * This pointer is used by the CAN driver to access the CAN1 Parity RAM 154 * for testing RAM parity error detect logic. 155 */ 156 #define canPARRAM1 (*(volatile uint32 *)(0xFF1E0000U + 0x10U)) 157 158 /** @def canPARRAM2 159 * @brief CAN2 Mailbox Parity RAM Pointer 160 * 161 * This pointer is used by the CAN driver to access the CAN2 Parity RAM 162 * for testing RAM parity error detect logic. 163 */ 164 #define canPARRAM2 (*(volatile uint32 *)(0xFF1C0000U + 0x10U)) 165 166 /** @def canPARRAM3 167 * @brief CAN3 Mailbox Parity RAM Pointer 168 * 169 * This pointer is used by the CAN driver to access the CAN3 Parity RAM 170 * for testing RAM parity error detect logic. 171 */ 172 #define canPARRAM3 (*(volatile uint32 *)(0xFF1A0000U + 0x10U)) 173 174 /* USER CODE BEGIN (1) */ 175 /* USER CODE END */ 176 177 178 #endif 179