1 /** @file reg_dmm.h 2 * @brief DMM Register Layer Header File 3 * @date 29.May.2013 4 * @version 03.05.02 5 * 6 * This file contains: 7 * - Definitions 8 * - Types 9 * - Interface Prototypes 10 * . 11 * which are relevant for the DMM driver. 12 */ 13 14 /* (c) Texas Instruments 2009-2013, All rights reserved. */ 15 16 #ifndef __REG_DMM_H__ 17 #define __REG_DMM_H__ 18 19 #include "sys_common.h" 20 #include "gio.h" 21 22 23 24 /* USER CODE BEGIN (0) */ 25 /* USER CODE END */ 26 27 /* Dmm Register Frame Definition */ 28 /** @struct dmmBase 29 * @brief DMM Base Register Definition 30 * 31 * This structure is used to access the DMM module registers. 32 */ 33 /** @typedef dmmBASE_t 34 * @brief DMM Register Frame Type Definition 35 * 36 * This type is used to access the DMM Registers. 37 */ 38 39 typedef volatile struct dmmBase 40 { 41 uint32 GLBCTRL; /**< 0x0000: Global control register 0 */ 42 uint32 INTSET; /**< 0x0004: DMM Interrupt Set Register */ 43 uint32 INTCLR; /**< 0x0008: DMM Interrupt Clear Register */ 44 uint32 INTLVL; /**< 0x000C: DMM Interrupt Level Register */ 45 uint32 INTFLG; /**< 0x0010: DMM Interrupt Flag Register */ 46 uint32 OFF1; /**< 0x0014: DMM Interrupt Offset 1 Register */ 47 uint32 OFF2; /**< 0x0018: DMM Interrupt Offset 2 Register */ 48 uint32 DDMDEST; /**< 0x001C: DMM Direct Data Mode Destination Register */ 49 uint32 DDMBL; /**< 0x0020: DMM Direct Data Mode Blocksize Register */ 50 uint32 DDMPT; /**< 0x0024: DMM Direct Data Mode Pointer Register */ 51 uint32 INTPT; /**< 0x0028: DMM Direct Data Mode Interrupt Pointer Register */ 52 uint32 DEST0REG1; /**< 0x002C: DMM Destination 0 Region 1 */ 53 uint32 DEST0BL1; /**< 0x0030: DMM Destination 0 Blocksize 1 */ 54 uint32 DEST0REG2; /**< 0x0034: DMM Destination 0 Region 2 */ 55 uint32 DEST0BL2; /**< 0x0038: DMM Destination 0 Blocksize 2 */ 56 uint32 DEST1REG1; /**< 0x003C: DMM Destination 1 Region 1 */ 57 uint32 DEST1BL1; /**< 0x0040: DMM Destination 1 Blocksize 1 */ 58 uint32 DEST1REG2; /**< 0x0044: DMM Destination 1 Region 2 */ 59 uint32 DEST1BL2; /**< 0x0048: DMM Destination 1 Blocksize 2 */ 60 uint32 DEST2REG1; /**< 0x004C: DMM Destination 2 Region 1 */ 61 uint32 DEST2BL1; /**< 0x0050: DMM Destination 2 Blocksize 1 */ 62 uint32 DEST2REG2; /**< 0x0054: DMM Destination 2 Region 2 */ 63 uint32 DEST2BL2; /**< 0x0058: DMM Destination 2 Blocksize 2 */ 64 uint32 DEST3REG1; /**< 0x005C: DMM Destination 3 Region 1 */ 65 uint32 DEST3BL1; /**< 0x0060: DMM Destination 3 Blocksize 1 */ 66 uint32 DEST3REG2; /**< 0x0064: DMM Destination 3 Region 2 */ 67 uint32 DEST3BL2; /**< 0x0068: DMM Destination 3 Blocksize 2 */ 68 uint32 PC0; /**< 0x006C: DMM Pin Control 0 */ 69 uint32 PC1; /**< 0x0070: DMM Pin Control 1 */ 70 uint32 PC2; /**< 0x0074: DMM Pin Control 2 */ 71 uint32 PC3; /**< 0x0078: DMM Pin Control 3 */ 72 uint32 PC4; /**< 0x007C: DMM Pin Control 4 */ 73 uint32 PC5; /**< 0x0080: DMM Pin Control 5 */ 74 uint32 PC6; /**< 0x0084: DMM Pin Control 6 */ 75 uint32 PC7; /**< 0x0088: DMM Pin Control 7 */ 76 uint32 PC8; /**< 0x008C: DMM Pin Control 8 */ 77 } dmmBASE_t; 78 79 80 /** @def dmmREG 81 * @brief DMM Register Frame Pointer 82 * 83 * This pointer is used by the DMM driver to access the DMM module registers. 84 */ 85 #define dmmREG ((dmmBASE_t *)0xFFFFF700U) 86 87 /** @def dmmPORT 88 * @brief DMM Port Register Pointer 89 * 90 * Pointer used by the GIO driver to access I/O PORT of DMM 91 * (use the GIO drivers to access the port pins). 92 */ 93 #define dmmPORT ((gioPORT_t *)0xFFFFF738U) 94 95 /* USER CODE BEGIN (1) */ 96 /* USER CODE END */ 97 98 99 #endif 100