1 /** @file reg_emif.h 2 * @brief EMIF Register Layer Header File 3 * @date 29.May.2013 4 * @version 03.05.02 5 * 6 * This file contains: 7 * - Definitions 8 * - Types 9 * - Interface Prototypes 10 * . 11 * which are relevant for the EMIF driver. 12 */ 13 14 /* (c) Texas Instruments 2009-2013, All rights reserved. */ 15 16 #ifndef __REG_EMIF_H__ 17 #define __REG_EMIF_H__ 18 19 #include "sys_common.h" 20 21 22 23 /* USER CODE BEGIN (0) */ 24 /* USER CODE END */ 25 26 /* Emif Register Frame Definition */ 27 /** @struct emifBASE_t 28 * @brief emifBASE Register Definition 29 * 30 * This structure is used to access the EMIF module registers. 31 */ 32 typedef volatile struct emifBase 33 { 34 uint32 MIDR; /**< 0x0000 Module ID Register */ 35 uint32 AWCC; /**< 0x0004 Asynchronous wait cycle register*/ 36 uint32 SDCR; /**< 0x0008 SDRAM configuration register */ 37 uint32 SDRCR ; /**< 0x000C Set Interrupt Enable Register */ 38 uint32 CE2CFG; /**< 0x0010 Asynchronous 1 Configuration Register */ 39 uint32 CE3CFG; /**< 0x0014 Asynchronous 2 Configuration Register */ 40 uint32 CE4CFG; /**< 0x0018 Asynchronous 3 Configuration Register */ 41 uint32 CE5CFG; /**< 0x001C Asynchronous 4 Configuration Register */ 42 uint32 SDTIMR; /**< 0x0020 SDRAM Timing Register */ 43 uint32 dummy1[6]; /** reserved **/ 44 uint32 SDSRETR; /**< 0x003c SDRAM Self Refresh Exit Timing Register */ 45 uint32 INTRAW; /**< 0x0040 0x0020 Interrupt Vector Offset*/ 46 uint32 INTMSK; /**< 0x0044 EMIF Interrupt Mask Register */ 47 uint32 INTMSKSET; /**< 48 EMIF Interrupt Mask Set Register */ 48 uint32 INTMSKCLR; /**< 0x004c EMIF Interrupt Mask Register */ 49 uint32 dummy2[6]; /** reserved **/ 50 uint32 PMCR; /**< 0x0068 Page Mode Control Register*/ 51 52 } emifBASE_t; 53 54 #define emifREG ((emifBASE_t *)0xFCFFE800U) 55 56 /* USER CODE BEGIN (1) */ 57 /* USER CODE END */ 58 59 60 #endif 61