1 /** @file reg_rtp.h 2 * @brief RTP Register Layer Header File 3 * @date 29.May.2013 4 * @version 03.05.02 5 * 6 * This file contains: 7 * - Definitions 8 * - Types 9 * - Interface Prototypes 10 * . 11 * which are relevant for the RTP driver. 12 */ 13 14 /* (c) Texas Instruments 2009-2013, All rights reserved. */ 15 16 #ifndef __REG_RTP_H__ 17 #define __REG_RTP_H__ 18 19 #include "sys_common.h" 20 #include "gio.h" 21 22 23 24 /* USER CODE BEGIN (0) */ 25 /* USER CODE END */ 26 27 /* Rtp Register Frame Definition */ 28 /** @struct rtpBase 29 * @brief RTP Base Register Definition 30 * 31 * This structure is used to access the RTP module registers. 32 */ 33 /** @typedef rtpBASE_t 34 * @brief RTP Register Frame Type Definition 35 * 36 * This type is used to access the RTP Registers. 37 */ 38 typedef volatile struct rtpBase 39 { 40 uint32 GLBCTRL; /**< 0x0000: RTP Global Control Register */ 41 uint32 TRENA; /**< 0x0004: RTP Trace Enable Register */ 42 uint32 GSR; /**< 0x0008: RTP Global Status Register */ 43 uint32 RAM1REG1; /**< 0x000C: RTP RAM 1 Trace Region 1 Register */ 44 uint32 RAM1REG2; /**< 0x0010: RTP RAM 1 Trace Region 2 Register */ 45 uint32 RAM2REG1; /**< 0x0014: RTP RAM 2 Trace Region 1 Register */ 46 uint32 RAM2REG2; /**< 0x0018: RTP RAM 2 Trace Region 2 Register */ 47 uint32 rsvd1[2U]; /**< 0x001C: Reserved */ 48 uint32 ERREG1; /**< 0x0024: RTP Peripheral Trace Region 1 Register */ 49 uint32 ERREG2; /**< 0x0028: RTP Peripheral Trace Region 2 Register */ 50 uint32 DDMW; /**< 0x002C: RTP Direct Data Mode Write Register */ 51 uint32 rsvd2; /**< 0x0030: Reserved */ 52 uint32 PC0; /**< 0x0034: RTP Pin Control 0 Register */ 53 uint32 PC1; /**< 0x0038: RTP Pin Control 1 Register */ 54 uint32 PC2; /**< 0x003C: RTP Pin Control 2 Register */ 55 uint32 PC3; /**< 0x0040: RTP Pin Control 3 Register */ 56 uint32 PC4; /**< 0x0044: RTP Pin Control 4 Register */ 57 uint32 PC5; /**< 0x0048: RTP Pin Control 5 Register */ 58 uint32 PC6; /**< 0x004C: RTP Pin Control 6 Register */ 59 uint32 PC7; /**< 0x0050: RTP Pin Control 7 Register */ 60 uint32 PC8; /**< 0x0054: RTP Pin Control 8 Register */ 61 } rtpBASE_t; 62 63 64 /** @def rtpREG 65 * @brief RTP Register Frame Pointer 66 * 67 * This pointer is used by the RTP driver to access the RTP module registers. 68 */ 69 #define rtpREG ((rtpBASE_t *)0xFFFFFA00U) 70 71 /** @def rtpPORT 72 * @brief RTP Port Register Pointer 73 * 74 * Pointer used by the GIO driver to access I/O PORT of RTP 75 * (use the GIO drivers to access the port pins). 76 */ 77 #define rtpPORT ((gioPORT_t *)0xFFFFFA38U) 78 79 /* USER CODE BEGIN (1) */ 80 /* USER CODE END */ 81 82 83 #endif 84