1 /** @file reg_sci.h 2 * @brief SCI Register Layer Header File 3 * @date 29.May.2013 4 * @version 03.05.02 5 * 6 * This file contains: 7 * - Definitions 8 * - Types 9 * - Interface Prototypes 10 * . 11 * which are relevant for the SCI driver. 12 */ 13 14 /* (c) Texas Instruments 2009-2013, All rights reserved. */ 15 16 #ifndef __REG_SCI_H__ 17 #define __REG_SCI_H__ 18 19 #include "sys_common.h" 20 #include "gio.h" 21 22 23 24 /* USER CODE BEGIN (0) */ 25 /* USER CODE END */ 26 27 /* Sci Register Frame Definition */ 28 /** @struct sciBase 29 * @brief SCI Base Register Definition 30 * 31 * This structure is used to access the SCI module registers. 32 */ 33 /** @typedef sciBASE_t 34 * @brief SCI Register Frame Type Definition 35 * 36 * This type is used to access the SCI Registers. 37 */ 38 typedef volatile struct sciBase 39 { 40 uint32 GCR0; /**< 0x0000 Global Control Register 0 */ 41 uint32 GCR1; /**< 0x0004 Global Control Register 1 */ 42 uint32 GCR2; /**< 0x0008 Global Control Register 2 */ 43 uint32 SETINT; /**< 0x000C Set Interrupt Enable Register */ 44 uint32 CLRINT; /**< 0x0010 Clear Interrupt Enable Register */ 45 uint32 SETINTLVL; /**< 0x0014 Set Interrupt Level Register */ 46 uint32 CLRINTLVL; /**< 0x0018 Set Interrupt Level Register */ 47 uint32 FLR; /**< 0x001C Interrupt Flag Register */ 48 uint32 INTVECT0; /**< 0x0020 Interrupt Vector Offset 0 */ 49 uint32 INTVECT1; /**< 0x0024 Interrupt Vector Offset 1 */ 50 uint32 FORMAT; /**< 0x0028 Format Control Register */ 51 uint32 BRS; /**< 0x002C Baud Rate Selection Register */ 52 uint32 ED; /**< 0x0030 Emulation Register */ 53 uint32 RD; /**< 0x0034 Receive Data Buffer */ 54 uint32 TD; /**< 0x0038 Transmit Data Buffer */ 55 uint32 FUN; /**< 0x003C Pin Function Register */ 56 uint32 DIR; /**< 0x0040 Pin Direction Register */ 57 uint32 DIN; /**< 0x0044 Pin Data In Register */ 58 uint32 DOUT; /**< 0x0048 Pin Data Out Register */ 59 uint32 SET; /**< 0x004C Pin Data Set Register */ 60 uint32 CLR; /**< 0x0050 Pin Data Clr Register */ 61 uint32 ODR; /**< 0x0054: Pin Open Drain Output Enable Register */ 62 uint32 PD; /**< 0x0058: Pin Pullup/Pulldown Disable Register */ 63 uint32 PSL; /**< 0x005C: Pin Pullup/Pulldown Selection Register */ 64 uint32 rsdv1[12U]; /**< 0x060: Reserved */ 65 uint32 IODFTCTRL; /**< 0x0090: I/O Error Enable Register */ 66 } sciBASE_t; 67 68 69 /** @def sciREG 70 * @brief Register Frame Pointer 71 * 72 * This pointer is used by the SCI driver to access the sci module registers. 73 */ 74 #define sciREG ((sciBASE_t *)0xFFF7E500U) 75 76 77 /** @def sciPORT 78 * @brief SCI GIO Port Register Pointer 79 * 80 * Pointer used by the GIO driver to access I/O PORT of SCI 81 * (use the GIO drivers to access the port pins). 82 */ 83 #define sciPORT ((gioPORT_t *)0xFFF7E540U) 84 85 86 /** @def scilinREG 87 * @brief SCILIN (LIN - Compatibility Mode) Register Frame Pointer 88 * 89 * This pointer is used by the SCI driver to access the sci module registers. 90 */ 91 #define scilinREG ((sciBASE_t *)0xFFF7E400U) 92 93 94 /** @def scilinPORT 95 * @brief SCILIN (LIN - Compatibility Mode) Register Frame Pointer 96 * 97 * Pointer used by the GIO driver to access I/O PORT of LIN 98 * (use the GIO drivers to access the port pins). 99 */ 100 #define scilinPORT ((gioPORT_t *)0xFFF7E440U) 101 102 /* USER CODE BEGIN (1) */ 103 /* USER CODE END */ 104 105 106 #endif 107