1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /*
3  * Copyright (c) 2019-2021 Rockchip Electronics Co., Ltd.
4  */
5 
6 #include "soc.h"
7 #include "hal_base.h"
8 #include "hal_def.h"
9 
10 /*----------------------------------------------------------------------------
11   Define clocks
12  *----------------------------------------------------------------------------*/
13 #define SYSTEM_CLOCK  (24000000U)
14 
15 /*----------------------------------------------------------------------------
16   Exception / Interrupt Vector table
17  *----------------------------------------------------------------------------*/
18 extern const VECTOR_TABLE_Type __VECTOR_TABLE[80];
19 
20 /*----------------------------------------------------------------------------
21   System Core Clock Variable
22  *----------------------------------------------------------------------------*/
23 uint32_t SystemCoreClock = SYSTEM_CLOCK;
24 
25 /*----------------------------------------------------------------------------
26   Externals
27  *----------------------------------------------------------------------------*/
CacheInit(void)28 void CacheInit(void)
29 {
30 #if defined(HAL_ICACHE_MODULE_ENABLED) || defined(HAL_DCACHE_MODULE_ENABLED)
31     uint32_t status;
32 #endif
33 
34 #if defined(HAL_ICACHE_MODULE_ENABLED)
35     /* config icache: mpu disable, stb disable, write through, hot buffer enable */
36     ICACHE->CACHE_CTRL |= (ICACHE_CACHE_CTRL_CACHE_EN_MASK | ICACHE_CACHE_CTRL_CACHE_WT_EN_MASK |
37                            ICACHE_CACHE_CTRL_CACHE_MPU_MODE_MASK);
38     ICACHE->CACHE_CTRL &= (~ICACHE_CACHE_CTRL_CACHE_STB_EN_MASK);
39 
40     do {
41         status =
42             ICACHE->CACHE_STATUS & ICACHE_CACHE_STATUS_CACHE_INIT_FINISH_MASK;
43     } while (status == 0);
44 
45     ICACHE->CACHE_CTRL &= ~ICACHE_CACHE_CTRL_CACHE_BYPASS_MASK;
46 #endif
47 
48 #if defined(HAL_DCACHE_MODULE_ENABLED)
49     /* stb enable, stb_entry=7, stb_timeout enable, write back */
50     DCACHE->CACHE_CTRL |= DCACHE_CACHE_CTRL_CACHE_EN_MASK |
51                           (7U << DCACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_SHIFT) |
52                           DCACHE_CACHE_CTRL_STB_TIMEOUT_EN_MASK |
53                           DCACHE_CACHE_CTRL_CACHE_MPU_MODE_MASK;
54     DCACHE->STB_TIMEOUT_CTRL = 1;
55 
56     do {
57         status =
58             DCACHE->CACHE_STATUS & DCACHE_CACHE_STATUS_CACHE_INIT_FINISH_MASK;
59     } while (status == 0);
60 
61     DCACHE->CACHE_CTRL &= ~DCACHE_CACHE_CTRL_CACHE_BYPASS_MASK;
62 
63     /* enable dap cache access for jtag protocol. don't modify the uncache data
64      * by jtag, the data will be inconsistent. */
65     GRF->MCU_CON0 |= GRF_MCU_CON0_M4_DAP_DCACHE_MASK;
66 #endif
67 }
68 
69 /*----------------------------------------------------------------------------
70   System Core Clock update function
71  *----------------------------------------------------------------------------*/
SystemCoreClockUpdate(void)72 void SystemCoreClockUpdate(void)
73 {
74     SystemCoreClock = SYSTEM_CLOCK;
75 }
76 
77 /*----------------------------------------------------------------------------
78   System initialization function
79  *----------------------------------------------------------------------------*/
SystemInit(void)80 void SystemInit(void)
81 {
82 
83 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
84   SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
85 #endif
86 
87 #if defined (__FPU_USED) && (__FPU_USED == 1U)
88   SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */
89                  (3U << 11U*2U)  );         /* enable CP11 Full Access */
90 #endif
91 
92 #ifdef UNALIGNED_SUPPORT_DISABLE
93   SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
94 #endif
95 
96     SystemCoreClock = SYSTEM_CLOCK;
97 }
98 
99