1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. 4 */ 5 6 #include "hal_conf.h" 7 8 #ifdef HAL_CRU_MODULE_ENABLED 9 10 /** @addtogroup RK_HAL_Driver 11 * @{ 12 */ 13 14 /** @addtogroup CRU 15 * @{ 16 */ 17 18 #ifndef _HAL_CRU_H_ 19 #define _HAL_CRU_H_ 20 21 #include "hal_def.h" 22 23 /*************************** MACRO Definition ****************************/ 24 /** @defgroup CRU_Exported_Definition_Group1 Basic Definition 25 * @{ 26 */ 27 28 #define MHZ 1000000 29 #define KHZ 1000 30 31 #ifndef PLL_INPUT_OSC_RATE 32 #define PLL_INPUT_OSC_RATE (24 * MHZ) 33 #endif 34 35 #define CLK_RESET_GET_REG_OFFSET(x) ((uint32_t)((x) / 16)) 36 #define CLK_RESET_GET_BITS_SHIFT(x) ((uint32_t)((x) % 16)) 37 38 #define CLK_GATE_GET_REG_OFFSET(x) ((uint32_t)((x) / 16)) 39 #define CLK_GATE_GET_BITS_SHIFT(x) ((uint32_t)((x) % 16)) 40 41 #define CLK_GET_MUX(x) ((x) & 0x0F0F00FFU) 42 #define CLK_GET_DIV(x) ((((x) & 0xFF00U) >> 8) | (((x) & 0xF0F00000U) >> 4)) 43 44 #define WIDTH_TO_MASK(width) ((1 << (width)) - 1) 45 46 #define CLK_MUX_REG_OFFSET_SHIFT 0U 47 #define CLK_MUX_REG_OFFSET_MASK 0x0000FFFFU 48 #define CLK_MUX_SHIFT_SHIFT 16U 49 #define CLK_MUX_SHIFT_MASK 0x00FF0000U 50 #define CLK_MUX_WIDTH_SHIFT 24U 51 #define CLK_MUX_WIDTH_MASK 0xFF000000U 52 53 #define CLK_MUX_GET_REG_OFFSET(x) \ 54 (((uint32_t)(x) & CLK_MUX_REG_OFFSET_MASK) >> CLK_MUX_REG_OFFSET_SHIFT) 55 #define CLK_MUX_GET_BITS_SHIFT(x) \ 56 (((uint32_t)(x) & CLK_MUX_SHIFT_MASK) >> CLK_MUX_SHIFT_SHIFT) 57 #define CLK_MUX_GET_MASK(x) \ 58 WIDTH_TO_MASK((((uint32_t)(x) & CLK_MUX_WIDTH_MASK) >> CLK_MUX_WIDTH_SHIFT)) \ 59 << CLK_MUX_GET_BITS_SHIFT(x) 60 61 #define CLK_DIV_REG_OFFSET_SHIFT 0U 62 #define CLK_DIV_REG_OFFSET_MASK 0x0000FFFFU 63 #define CLK_DIV_SHIFT_SHIFT 16U 64 #define CLK_DIV_SHIFT_MASK 0x00FF0000U 65 #define CLK_DIV_WIDTH_SHIFT 24U 66 #define CLK_DIV_WIDTH_MASK 0xFF000000U 67 68 #define CLK_DIV_GET_REG_OFFSET(x) \ 69 (((uint32_t)(x) & CLK_DIV_REG_OFFSET_MASK) >> CLK_DIV_REG_OFFSET_SHIFT) 70 #define CLK_DIV_GET_BITS_SHIFT(x) \ 71 (((uint32_t)(x) & CLK_DIV_SHIFT_MASK) >> CLK_DIV_SHIFT_SHIFT) 72 #define CLK_DIV_GET_MASK(x) \ 73 WIDTH_TO_MASK((((uint32_t)(x) & CLK_DIV_WIDTH_MASK) >> CLK_DIV_WIDTH_SHIFT)) \ 74 << CLK_DIV_GET_BITS_SHIFT(x) 75 76 #define RK_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, \ 77 _frac) \ 78 { \ 79 .rate = _rate##U, .fbDiv = _fbdiv, .postDiv1 = _postdiv1, \ 80 .refDiv = _refdiv, .postDiv2 = _postdiv2, .dsmpd = _dsmpd, \ 81 .frac = _frac, \ 82 } 83 84 struct PLL_CONFIG { 85 uint32_t rate; 86 uint32_t fbDiv; 87 uint32_t postDiv1; 88 uint32_t refDiv; 89 uint32_t postDiv2; 90 uint32_t dsmpd; 91 uint32_t frac; 92 }; 93 94 struct PLL_SETUP { 95 __IO uint32_t *conOffset0; 96 __IO uint32_t *conOffset1; 97 __IO uint32_t *conOffset2; 98 __IO uint32_t *conOffset3; 99 __IO uint32_t *modeOffset; 100 __I uint32_t *stat0; 101 uint32_t modeShift; 102 uint32_t lockShift; 103 uint32_t modeMask; 104 const struct PLL_CONFIG *rateTable; 105 }; 106 107 typedef enum { 108 GLB_SRST_FST = 0xfdb9, 109 GLB_SRST_SND = 0xeca8, 110 } eCRU_GlbSrstType; 111 112 typedef enum { 113 GLB_RST_FST_WDT0 = 0U, 114 GLB_RST_SND_WDT0, 115 GLB_RST_FST_WDT1, 116 GLB_RST_SND_WDT1, 117 GLB_RST_FST_WDT2, 118 GLB_RST_SND_WDT2, 119 } eCRU_WdtRstType; 120 121 /***************************** Structure Definition **************************/ 122 123 /** @} */ 124 /***************************** Function Declare ******************************/ 125 /** @defgroup CRU_Public_Function_Declare Public Function Declare 126 * @{ 127 */ 128 uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup); 129 HAL_Status HAL_CRU_SetPllFreq(struct PLL_SETUP *pSetup, uint32_t rate); 130 HAL_Status HAL_CRU_SetPllPowerUp(struct PLL_SETUP *pSetup); 131 HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup); 132 133 HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk); 134 HAL_Status HAL_CRU_ClkEnable(uint32_t clk); 135 HAL_Status HAL_CRU_ClkDisable(uint32_t clk); 136 137 HAL_Check HAL_CRU_ClkIsReset(uint32_t clk); 138 HAL_Status HAL_CRU_ClkResetAssert(uint32_t clk); 139 HAL_Status HAL_CRU_ClkResetDeassert(uint32_t clk); 140 141 HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue); 142 uint32_t HAL_CRU_ClkGetDiv(uint32_t divName); 143 144 HAL_Status HAL_CRU_ClkSetMux(uint32_t muxName, uint32_t muxValue); 145 uint32_t HAL_CRU_ClkGetMux(uint32_t muxName); 146 147 HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate, 148 uint32_t *numerator, 149 uint32_t *denominator); 150 151 uint32_t HAL_CRU_ClkGetFreq(eCLOCK_Name clockName); 152 HAL_Status HAL_CRU_ClkSetFreq(eCLOCK_Name clockName, uint32_t rate); 153 154 HAL_Status HAL_CRU_VopDclkEnable(uint32_t gateId); 155 HAL_Status HAL_CRU_VopDclkDisable(uint32_t gateId); 156 157 HAL_Status HAL_CRU_ClkNp5BestDiv(eCLOCK_Name clockName, uint32_t rate, uint32_t pRate, uint32_t *bestdiv); 158 159 HAL_Status HAL_CRU_SetGlbSrst(eCRU_GlbSrstType type); 160 161 HAL_Status HAL_CRU_WdtGlbRstEnable(eCRU_WdtRstType wdtType); 162 163 HAL_Status HAL_CRU_PllCompensation(eCLOCK_Name clockName, int ppm); 164 165 #ifdef HAL_CRU_AS_FEATURE_ENABLED 166 /** 167 * @brief it is for AS init. 168 */ 169 void HAL_CRU_AsInit(void); 170 171 /** 172 * @brief it is for AS enable. 173 * @param ch: channel 174 * @param en: 1 is enable, 0 is disable. 175 */ 176 void HAL_CRU_AsEnable(uint8_t ch, uint8_t en); 177 #endif 178 179 /** @} */ 180 181 #endif 182 183 /** @} */ 184 185 /** @} */ 186 187 #endif /* HAL_CRU_MODULE_ENABLED */ 188