1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. 4 */ 5 6 /** @addtogroup RK_HAL_Driver 7 * @{ 8 */ 9 10 /** @addtogroup HAL_DEF 11 * @{ 12 */ 13 14 #ifndef _HAL_DEF_H_ 15 #define _HAL_DEF_H_ 16 17 #include <stdio.h> 18 #include <stdlib.h> 19 #include <string.h> 20 #include <stdarg.h> 21 #include <stdint.h> 22 #include <stdbool.h> 23 24 #include "cmsis_compiler.h" 25 #include "soc.h" 26 #include "hal_list.h" 27 28 /***************************** MACRO Definition ******************************/ 29 /** @defgroup HAL_DEF_Exported_Definition_Group1 Basic Definition 30 * @{ 31 */ 32 33 #define SET_BIT(REG, BIT) ((*(volatile uint32_t *)&(REG)) |= (BIT)) /**< Set 1 to the register specific bit field */ 34 #define CLEAR_BIT(REG, MASK) ((*(volatile uint32_t *)&(REG)) &= ~(MASK)) /**< Clear the specific bits filed from the register */ 35 #define READ_BIT(REG, MASK) ((*(volatile const uint32_t *)&(REG)) & (MASK)) /**< Read the value of a specific bits field from the register */ 36 #define CLEAR_REG(REG) ((*(volatile uint32_t *)&(REG)) = (0x0)) /**< Write 0 to the register */ 37 #define WRITE_REG(REG, VAL) ((*(volatile uint32_t *)&(REG)) = (VAL)) /**< Write the register */ 38 #define READ_REG(REG) ((*(volatile const uint32_t *)&(REG))) /**< Read the register */ 39 #define MODIFY_REG(REG, CLEARMASK, SETMASK) \ 40 WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) /**< Clear and set the value of a specific bits field from the register */ 41 #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) 42 43 #if defined(__GNUC__) || defined(__CC_ARM) 44 #define MASK_TO_WE(msk) (__builtin_constant_p(msk) ? ((msk) > 0xFFFFU ? 0 : ((msk) << 16)) : ((msk) << 16)) 45 #else 46 #define MASK_TO_WE(msk) ((msk) << 16) 47 #endif 48 #define VAL_MASK_WE(msk, val) ((MASK_TO_WE(msk)) | (val)) 49 #define WRITE_REG_MASK_WE(reg, msk, val) WRITE_REG(reg, (VAL_MASK_WE(msk, val))) 50 51 /* Misc OPS Marco */ 52 #define HAL_MAX_DELAY 0xFFFFFFFFU 53 54 #define RESET 0 55 #define HAL_IS_BIT_SET(REG, MASK) (((*(volatile uint32_t *)&(REG)) & (MASK)) != RESET) /**< Check if the the specific bits filed from the register is valid */ 56 #define HAL_IS_BIT_CLR(REG, MASK) (((*(volatile uint32_t *)&(REG)) & (MASK)) == RESET) /**< Check if the the specific bits filed from the register is isvalid */ 57 58 #define HAL_BIT(nr) (1UL << (nr)) 59 #define HAL_ARRAY_SIZE(a) (sizeof((a)) / sizeof((a)[0])) 60 #define HAL_MAX(x, y) ((x) > (y) ? (x) : (y)) 61 #define HAL_MIN(x, y) ((x) < (y) ? (x) : (y)) 62 63 #define HAL_DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) 64 65 #define HAL_IS_ALIGNED(x, a) (((x) & (a - 1)) == 0) 66 #ifdef CACHE_LINE_SIZE 67 #define HAL_IS_CACHELINE_ALIGNED(x) HAL_IS_ALIGNED((uint32_t)(x), CACHE_LINE_SIZE) 68 #else 69 #define HAL_IS_CACHELINE_ALIGNED(x) HAL_IS_ALIGNED((uint32_t)(x), 4) 70 #endif 71 72 /* Compiller Macro */ 73 #if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) || defined(__ICCARM__) 74 #define HAL_UNUSED __attribute__((__unused__)) 75 #else 76 #define HAL_UNUSED 77 #endif 78 79 #ifdef CACHE_LINE_SIZE 80 #define HAL_CACHELINE_ALIGNED __ALIGNED(CACHE_LINE_SIZE) 81 #else 82 #define HAL_CACHELINE_ALIGNED 83 #endif 84 85 #ifdef HAL_SRAM_SECTION_ENABLED 86 #define HAL_SECTION_SRAM_CODE __attribute__((section(".sram_code"))) 87 #define HAL_SECTION_SRAM_RODATA __attribute__((section(".sram_rodata"))) 88 #define HAL_SECTION_SRAM_DATA __attribute__((section(".sram_data"))) 89 #define HAL_SECTION_SRAM_BSS __attribute__((section(".sram_bss"))) 90 #else 91 #define HAL_SECTION_SRAM_CODE 92 #define HAL_SECTION_SRAM_RODATA 93 #define HAL_SECTION_SRAM_DATA 94 #define HAL_SECTION_SRAM_BSS 95 #endif 96 97 #ifdef HAL_PSRAM_SECTION_ENABLED 98 #define HAL_SECTION_PSRAM_CODE __attribute__((section(".psram_code"))) 99 #define HAL_SECTION_PSRAM_RODATA __attribute__((section(".psram_rodata"))) 100 #define HAL_SECTION_PSRAM_DATA __attribute__((section(".psram_data"))) 101 #define HAL_SECTION_PSRAM_BSS __attribute__((section(".psram_bss"))) 102 #else 103 #define HAL_SECTION_PSRAM_CODE 104 #define HAL_SECTION_PSRAM_RODATA 105 #define HAL_SECTION_PSRAM_DATA 106 #define HAL_SECTION_PSRAM_BSS 107 #endif 108 109 #ifdef HAL_XIP_SECTION_ENABLED 110 #define HAL_SECTION_XIP_CODE __attribute__((section(".xip_code"))) 111 #define HAL_SECTION_XIP_RODATA __attribute__((section(".xip_rodata"))) 112 #else 113 #define HAL_SECTION_XIP_CODE 114 #define HAL_SECTION_XIP_RODATA 115 #endif 116 117 /** MCU systick clock source */ 118 typedef enum { 119 HAL_SYSTICK_CLKSRC_CORE, 120 HAL_SYSTICK_CLKSRC_EXT 121 } eHAL_systickClkSource; 122 123 /** Check if is MCU systick clock source */ 124 #define IS_SYSTICK_SOURCE(s) (((s) == HAL_SYSTICK_CLKSRC_CORE) || ((s) == HAL_SYSTICK_CLKSRC_EXT)) 125 126 /***************************** Structure Definition **************************/ 127 /** HAL boolean type definition */ 128 typedef enum { 129 HAL_FALSE = 0x00U, 130 HAL_TRUE = 0x01U 131 } HAL_Check; 132 133 /** HAL error code definition */ 134 typedef enum { 135 HAL_OK = 0x00U, 136 HAL_ERROR = (-1), 137 HAL_BUSY = (-16), 138 HAL_NODEV = (-19), 139 HAL_INVAL = (-22), 140 HAL_NOSYS = (-38), 141 HAL_TIMEOUT = (-110) 142 } HAL_Status; 143 144 /** HAL functional status definition */ 145 typedef enum { 146 HAL_DISABLE = 0x00U, 147 HAL_ENABLE = 0x01U 148 } HAL_FuncStatus; 149 150 /** HAL lock structures definition */ 151 typedef enum { 152 HAL_UNLOCKED = 0x00U, 153 HAL_LOCKED = 0x01U 154 } HAL_LockStatus; 155 156 /** RK GPIO bank definition */ 157 typedef enum { 158 #ifdef GPIO0 159 GPIO_BANK0 = 0, 160 #endif 161 #ifdef GPIO1 162 GPIO_BANK1 = 1, 163 #endif 164 #ifdef GPIO2 165 GPIO_BANK2 = 2, 166 #endif 167 #ifdef GPIO3 168 GPIO_BANK3 = 3, 169 #endif 170 #ifdef GPIO4 171 GPIO_BANK4 = 4, 172 #endif 173 GPIO_BANK_NUM 174 } eGPIO_bankId; 175 176 /** HAL function type definition */ 177 typedef void (*pFunc)(void); 178 179 /** @} */ 180 /***************************** Function Declare ******************************/ 181 182 #endif 183 184 /** @} */ 185 186 /** @} */ 187