1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2019-2021 Rockchip Electronics Co., Ltd. 4 */ 5 6 #include "hal_conf.h" 7 8 #ifdef HAL_DWDMA_MODULE_ENABLED 9 10 /** @addtogroup RK_HAL_Driver 11 * @{ 12 */ 13 14 /** @addtogroup DWDMA 15 * @{ 16 */ 17 18 #ifndef _HAL_DWDMA_H 19 #define _HAL_DWDMA_H 20 21 #include "hal_def.h" 22 23 /** @defgroup DWDMA_Exported_Definition_Group1 Basic Definition 24 * @{ 25 */ 26 27 /***************************** MACRO Definition ******************************/ 28 29 #define NR_DESCS_PER_CHANNEL 8 30 #define DMA_MAX_CHANNELS 8 31 32 /* Bitfields in CTL_LO */ 33 #define DWC_CTLL_INT_EN (1 << 0) /**< irqs enabled? */ 34 #define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /**< bytes per element */ 35 #define DWC_CTLL_SRC_WIDTH(n) ((n)<<4) 36 #define DWC_CTLL_DST_INC (0<<7) /**< DAR update/not */ 37 #define DWC_CTLL_DST_DEC (1<<7) 38 #define DWC_CTLL_DST_FIX (2<<7) 39 #define DWC_CTLL_SRC_INC (0<<7) /**< SAR update/not */ 40 #define DWC_CTLL_SRC_DEC (1<<9) 41 #define DWC_CTLL_SRC_FIX (2<<9) 42 #define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /**< burst, \#elements */ 43 #define DWC_CTLL_SRC_MSIZE(n) ((n)<<14) 44 #define DWC_CTLL_S_GATH_EN (1 << 17) /**< src gather, !FIX */ 45 #define DWC_CTLL_D_SCAT_EN (1 << 18) /**< dst scatter, !FIX */ 46 #define DWC_CTLL_FC(n) ((n) << 20) 47 #define DWC_CTLL_FC_M2M (0 << 20) /**< mem-to-mem */ 48 #define DWC_CTLL_FC_M2P (1 << 20) /**< mem-to-periph */ 49 #define DWC_CTLL_FC_P2M (2 << 20) /**< periph-to-mem */ 50 #define DWC_CTLL_FC_P2P (3 << 20) /**< periph-to-periph */ 51 /* plus 4 transfer types for peripheral-as-flow-controller */ 52 #define DWC_CTLL_DMS(n) ((n)<<23) /**< dst master select */ 53 #define DWC_CTLL_SMS(n) ((n)<<25) /**< src master select */ 54 #define DWC_CTLL_LLP_D_EN (1 << 27) /**< dest block chain */ 55 #define DWC_CTLL_LLP_S_EN (1 << 28) /**< src block chain */ 56 57 /* Bitfields in CTL_HI */ 58 #define DWC_CTLH_DONE 0x00001000 59 #define DWC_CTLH_BLOCK_TS_MASK 0x00000fff 60 61 /* Bitfields in CFG_LO */ 62 #define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /**< priority mask */ 63 #define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /**< priority */ 64 #define DWC_CFGL_CH_SUSP (1 << 8) /**< pause xfer */ 65 #define DWC_CFGL_FIFO_EMPTY (1 << 9) /**< pause xfer */ 66 #define DWC_CFGL_HS_DST (1 << 10) /**< handshake w/dst */ 67 #define DWC_CFGL_HS_SRC (1 << 11) /**< handshake w/src */ 68 #define DWC_CFGL_LOCK_CH_XFER (0 << 12) /**< scope of LOCK_CH */ 69 #define DWC_CFGL_LOCK_CH_BLOCK (1 << 12) 70 #define DWC_CFGL_LOCK_CH_XACT (2 << 12) 71 #define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /**< scope of LOCK_BUS */ 72 #define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14) 73 #define DWC_CFGL_LOCK_BUS_XACT (2 << 14) 74 #define DWC_CFGL_LOCK_CH (1 << 15) /**< channel lockout */ 75 #define DWC_CFGL_LOCK_BUS (1 << 16) /**< busmaster lockout */ 76 #define DWC_CFGL_HS_DST_POL (1 << 18) /**< dst handshake active low */ 77 #define DWC_CFGL_HS_SRC_POL (1 << 19) /**< src handshake active low */ 78 #define DWC_CFGL_MAX_BURST(x) ((x) << 20) 79 #define DWC_CFGL_RELOAD_SAR (1 << 30) 80 #define DWC_CFGL_RELOAD_DAR (1 << 31) 81 82 /* Bitfields in CFG_HI */ 83 #define DWC_CFGH_FCMODE (1 << 0) 84 #define DWC_CFGH_FIFO_MODE (1 << 1) 85 #define DWC_CFGH_PROTCTL(x) ((x) << 2) 86 #define DWC_CFGH_DS_UPD_EN (1 << 5) 87 #define DWC_CFGH_SS_UPD_EN (1 << 6) 88 #define DWC_CFGH_SRC_PER(x) ((x) << 7) 89 #define DWC_CFGH_DST_PER(x) ((x) << 11) 90 91 /* Bitfields in SGR */ 92 #define DWC_SGR_SGI(x) ((x) << 0) 93 #define DWC_SGR_SGC(x) ((x) << 20) 94 95 /* Bitfields in DSR */ 96 #define DWC_DSR_DSI(x) ((x) << 0) 97 #define DWC_DSR_DSC(x) ((x) << 20) 98 99 /* Bitfields in CFG */ 100 #define DW_CFG_DMA_EN (1 << 0) 101 102 /* bursts size */ 103 typedef enum { 104 DWDMA_MSIZE_1, 105 DWDMA_MSIZE_4, 106 DWDMA_MSIZE_8, 107 DWDMA_MSIZE_16, 108 DWDMA_MSIZE_32, 109 DWDMA_MSIZE_64, 110 DWDMA_MSIZE_128, 111 DWDMA_MSIZE_256, 112 } eDWDMA_MSIZE; 113 114 /***************************** Structure Definition **************************/ 115 116 /** 117 * LLI == Linked List Item; a.k.a. DMA block descriptor 118 */ 119 struct DW_LLI { 120 uint32_t sar; /**< values that are not changed by hardware */ 121 uint32_t dar; /**< values that are not changed by hardware */ 122 uint32_t llp; /**< chain to next lli */ 123 uint32_t ctllo; 124 uint32_t ctlhi; 125 126 uint32_t sstat; /**< values that may get written back. */ 127 uint32_t dstat; /**< values that may get written back. */ 128 }; 129 130 /** 131 * struct DW_DESC - dma transfer desc 132 */ 133 struct DW_DESC { 134 struct DW_LLI lli; /**< FIRST values the hardware uses, must be in the first place. */ 135 136 uint32_t len; 137 }; 138 139 /** 140 * struct DWDMA_CHAN - dw dma channel. 141 */ 142 struct DWDMA_CHAN { 143 struct HAL_DWDMA_DEV *dw; 144 struct DMA_CHAN_REGS *creg; 145 struct DMA_SLAVE_CONFIG config; 146 struct DW_DESC *desc; 147 eDMA_TRANSFER_DIRECTION direction; 148 149 uint8_t mask; 150 uint8_t srcMaster; 151 uint8_t dstMaster; 152 uint8_t periId; 153 uint8_t chanId; 154 155 bool cyclic; 156 bool paused; 157 158 DMA_Callback callback; 159 void *cparam; 160 }; 161 162 /** 163 * struct HAL_DWDMA_DEV - dw dma hal dev. 164 */ 165 struct HAL_DWDMA_DEV { 166 struct DMA_REG *pReg; 167 struct DWDMA_CHAN chan[DMA_MAX_CHANNELS]; 168 uint8_t irq[DMA_MAX_CHANNELS]; 169 uint8_t allChanMask; 170 uint8_t used; 171 uint8_t maxChans; 172 /* hardware configuration */ 173 uint8_t dataWidth; 174 uint32_t blockSize; 175 176 void *priv; 177 }; 178 179 /** @} */ 180 181 /***************************** Function Declare ******************************/ 182 /** @defgroup DWDMA_Public_Function_Declare Public Function Declare 183 * @{ 184 */ 185 186 uint32_t HAL_DWDMA_GetRawBlockStatus(struct HAL_DWDMA_DEV *dw); 187 uint32_t HAL_DWDMA_GetRawErrStatus(struct HAL_DWDMA_DEV *dw); 188 uint32_t HAL_DWDMA_GetRawXferStatus(struct HAL_DWDMA_DEV *dw); 189 190 HAL_Status HAL_DWDMA_Init(struct HAL_DWDMA_DEV *dw); 191 HAL_Status HAL_DWDMA_DeInit(struct HAL_DWDMA_DEV *dw); 192 193 HAL_Status HAL_DWDMA_Start(struct DWDMA_CHAN *dwc); 194 HAL_Status HAL_DWDMA_Stop(struct DWDMA_CHAN *dwc); 195 HAL_Status HAL_DWDMA_Pause(struct DWDMA_CHAN *dwc); 196 HAL_Status HAL_DWDMA_Resume(struct DWDMA_CHAN *dwc); 197 198 struct DWDMA_CHAN *HAL_DWDMA_RequestChannel(struct HAL_DWDMA_DEV *dma, DMA_REQ_Type id); 199 HAL_Status HAL_DWDMA_ReleaseChannel(struct DWDMA_CHAN *dwc); 200 201 HAL_Status HAL_DWDMA_Config(struct DWDMA_CHAN *dwc, struct DMA_SLAVE_CONFIG *config); 202 HAL_Status HAL_DWDMA_PrepDmaMemcpy(struct DWDMA_CHAN *dwc, uint32_t dst, 203 uint32_t src, uint32_t len, 204 DMA_Callback callback, void *cparam); 205 HAL_Status HAL_DWDMA_PrepDmaCyclic(struct DWDMA_CHAN *dwc, uint32_t dmaAddr, 206 uint32_t len, uint32_t periodLen, 207 eDMA_TRANSFER_DIRECTION direction, 208 DMA_Callback callback, void *cparam); 209 HAL_Status HAL_DWDMA_PrepDmaSingle(struct DWDMA_CHAN *dwc, uint32_t dmaAddr, 210 uint32_t len, 211 eDMA_TRANSFER_DIRECTION direction, 212 DMA_Callback callback, void *cparam); 213 214 uint32_t HAL_DWDMA_IrqHandler(struct HAL_DWDMA_DEV *dw, uint32_t chanId); 215 uint32_t HAL_DWDMA_HandleChan(struct HAL_DWDMA_DEV *dw, uint32_t chanId); 216 struct DWDMA_CHAN *HAL_DWDMA_GetChannel(struct HAL_DWDMA_DEV *dw, uint32_t chanId); 217 218 /** @} */ 219 220 #endif 221 222 /** @} */ 223 224 /** @} */ 225 226 #endif /* HAL_DWDMA_MODULE_ENABLED */ 227