1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. 4 */ 5 6 #include "hal_conf.h" 7 8 /** @addtogroup RK_HAL_Driver 9 * @{ 10 */ 11 12 /** @addtogroup PINCTRL 13 * @{ 14 */ 15 16 #ifndef __HAL_PINCTRL_H__ 17 #define __HAL_PINCTRL_H__ 18 19 #include "hal_def.h" 20 21 /***************************** MACRO Definition ******************************/ 22 /** @defgroup PINCTRL_Exported_Definition_Group1 Basic Definition 23 * @{ 24 */ 25 26 /** PINCTRL IOFUNC Select definition */ 27 typedef enum { 28 IOFUNC_SEL_M0, 29 IOFUNC_SEL_M1, 30 IOFUNC_SEL_M2, 31 } eIOFUNC_SEL; 32 33 typedef enum { 34 #if defined(GPIO0) 35 GPIO0_A0 = 0, 36 GPIO0_A1, 37 GPIO0_A2, 38 GPIO0_A3, 39 GPIO0_A4, 40 GPIO0_A5, 41 GPIO0_A6, 42 GPIO0_A7, 43 GPIO0_B0 = 8, 44 GPIO0_B1, 45 GPIO0_B2, 46 GPIO0_B3, 47 GPIO0_B4, 48 GPIO0_B5, 49 GPIO0_B6, 50 GPIO0_B7, 51 GPIO0_C0 = 16, 52 GPIO0_C1, 53 GPIO0_C2, 54 GPIO0_C3, 55 GPIO0_C4, 56 GPIO0_C5, 57 GPIO0_C6, 58 GPIO0_C7, 59 GPIO0_D0 = 24, 60 GPIO0_D1, 61 GPIO0_D2, 62 GPIO0_D3, 63 GPIO0_D4, 64 GPIO0_D5, 65 GPIO0_D6, 66 GPIO0_D7, 67 #endif 68 #if defined(GPIO1) 69 GPIO1_A0 = 32, 70 GPIO1_A1, 71 GPIO1_A2, 72 GPIO1_A3, 73 GPIO1_A4, 74 GPIO1_A5, 75 GPIO1_A6, 76 GPIO1_A7, 77 GPIO1_B0 = 40, 78 GPIO1_B1, 79 GPIO1_B2, 80 GPIO1_B3, 81 GPIO1_B4, 82 GPIO1_B5, 83 GPIO1_B6, 84 GPIO1_B7, 85 GPIO1_C0 = 48, 86 GPIO1_C1, 87 GPIO1_C2, 88 GPIO1_C3, 89 GPIO1_C4, 90 GPIO1_C5, 91 GPIO1_C6, 92 GPIO1_C7, 93 GPIO1_D0 = 56, 94 GPIO1_D1, 95 GPIO1_D2, 96 GPIO1_D3, 97 GPIO1_D4, 98 GPIO1_D5, 99 GPIO1_D6, 100 GPIO1_D7, 101 #endif 102 #if defined(GPIO2) 103 GPIO2_A0 = 64, 104 GPIO2_A1, 105 GPIO2_A2, 106 GPIO2_A3, 107 GPIO2_A4, 108 GPIO2_A5, 109 GPIO2_A6, 110 GPIO2_A7, 111 GPIO2_B0 = 72, 112 GPIO2_B1, 113 GPIO2_B2, 114 GPIO2_B3, 115 GPIO2_B4, 116 GPIO2_B5, 117 GPIO2_B6, 118 GPIO2_B7, 119 GPIO2_C0 = 80, 120 GPIO2_C1, 121 GPIO2_C2, 122 GPIO2_C3, 123 GPIO2_C4, 124 GPIO2_C5, 125 GPIO2_C6, 126 GPIO2_C7, 127 GPIO2_D0 = 88, 128 GPIO2_D1, 129 GPIO2_D2, 130 GPIO2_D3, 131 GPIO2_D4, 132 GPIO2_D5, 133 GPIO2_D6, 134 GPIO2_D7, 135 #endif 136 #if defined(GPIO3) 137 GPIO3_A0 = 96, 138 GPIO3_A1, 139 GPIO3_A2, 140 GPIO3_A3, 141 GPIO3_A4, 142 GPIO3_A5, 143 GPIO3_A6, 144 GPIO3_A7, 145 GPIO3_B0 = 104, 146 GPIO3_B1, 147 GPIO3_B2, 148 GPIO3_B3, 149 GPIO3_B4, 150 GPIO3_B5, 151 GPIO3_B6, 152 GPIO3_B7, 153 GPIO3_C0 = 112, 154 GPIO3_C1, 155 GPIO3_C2, 156 GPIO3_C3, 157 GPIO3_C4, 158 GPIO3_C5, 159 GPIO3_C6, 160 GPIO3_C7, 161 GPIO3_D0 = 120, 162 GPIO3_D1, 163 GPIO3_D2, 164 GPIO3_D3, 165 GPIO3_D4, 166 GPIO3_D5, 167 GPIO3_D6, 168 GPIO3_D7, 169 #endif 170 #if defined(GPIO4) 171 GPIO4_A0 = 128, 172 GPIO4_A1, 173 GPIO4_A2, 174 GPIO4_A3, 175 GPIO4_A4, 176 GPIO4_A5, 177 GPIO4_A6, 178 GPIO4_A7, 179 GPIO4_B0 = 136, 180 GPIO4_B1, 181 GPIO4_B2, 182 GPIO4_B3, 183 GPIO4_B4, 184 GPIO4_B5, 185 GPIO4_B6, 186 GPIO4_B7, 187 GPIO4_C0 = 144, 188 GPIO4_C1, 189 GPIO4_C2, 190 GPIO4_C3, 191 GPIO4_C4, 192 GPIO4_C5, 193 GPIO4_C6, 194 GPIO4_C7, 195 GPIO4_D0 = 152, 196 GPIO4_D1, 197 GPIO4_D2, 198 GPIO4_D3, 199 GPIO4_D4, 200 GPIO4_D5, 201 GPIO4_D6, 202 GPIO4_D7, 203 #endif 204 GPIO_NUM_MAX 205 } ePINCTRL_PIN; 206 207 /** PINCTRL IOMUX definition */ 208 typedef enum { 209 PINCTRL_IOMUX_FUNC0, 210 PINCTRL_IOMUX_FUNC1, 211 PINCTRL_IOMUX_FUNC2, 212 PINCTRL_IOMUX_FUNC3, 213 PINCTRL_IOMUX_FUNC4, 214 PINCTRL_IOMUX_FUNC5, 215 PINCTRL_IOMUX_FUNC6, 216 PINCTRL_IOMUX_FUNC7 217 } ePINCTRL_iomuxFunc; 218 219 /** PINCTRL PULL definition */ 220 typedef enum { 221 PINCTRL_PULL_OD, 222 PINCTRL_PULL_UP, 223 PINCTRL_PULL_DOWN, 224 PINCTRL_PULL_KEEP 225 } ePINCTRL_pullMode; 226 227 /** PINCTRL Drive Strength definition */ 228 typedef enum { 229 PINCTRL_DRIVE_LEVEL0, 230 PINCTRL_DRIVE_LEVEL1, 231 PINCTRL_DRIVE_LEVEL2, 232 PINCTRL_DRIVE_LEVEL3, 233 PINCTRL_DRIVE_LEVEL4, 234 PINCTRL_DRIVE_LEVEL5, 235 PINCTRL_DRIVE_LEVEL6, 236 PINCTRL_DRIVE_LEVEL7 237 } ePINCTRL_driveLevel; 238 239 /** PINCTRL Slew Rate definition */ 240 typedef enum { 241 PINCTRL_SLEWRATE_SLOW, 242 PINCTRL_SLEWRATE_FAST 243 } ePINCTRL_slewRate; 244 245 /** PINCTRL Schmitt enable definition */ 246 typedef enum { 247 PINCTRL_SCHMITT_DIS, 248 PINCTRL_SCHMITT_EN 249 } ePINCTRL_schmitt; 250 251 #define FLAG_MUX HAL_BIT(31) 252 #define FLAG_PUL HAL_BIT(30) 253 #define FLAG_DRV HAL_BIT(29) 254 #define FLAG_SRT HAL_BIT(28) 255 #define FLAG_SMT HAL_BIT(27) 256 #define SHIFT_MUX (0) 257 #define SHIFT_PUL (4) 258 #define SHIFT_DRV (8) 259 #define SHIFT_SRT (16) 260 #define SHIFT_SMT (18) 261 #define MASK_MUX (0xFU << SHIFT_MUX) 262 #define MASK_PUL (0xFU << SHIFT_PUL) 263 #define MASK_DRV (0xFFU << SHIFT_DRV) 264 #define MASK_SRT (0x3U << SHIFT_SRT) 265 #define MASK_SMT (0x3U << SHIFT_SMT) 266 267 /** @brief PIN Configuration Mode 268 * Elements values convention: gggg g000 0000 ttrr dddd dddd pppp xxxx 269 * - ggggg : Flag to set Mux/Pull/Drive/Slewrate/Schmitt 270 * - tt : Schmitt value 271 * - rr : Slewrate value 272 * - dddddddd : Drive value 273 * - pppp : Pull value 274 * - xxxx : Mux mode value 275 */ 276 typedef enum { 277 PIN_CONFIG_MUX_FUNC0 = (0x0 << SHIFT_MUX | FLAG_MUX), 278 PIN_CONFIG_MUX_FUNC1 = (0x1 << SHIFT_MUX | FLAG_MUX), 279 PIN_CONFIG_MUX_FUNC2 = (0x2 << SHIFT_MUX | FLAG_MUX), 280 PIN_CONFIG_MUX_FUNC3 = (0x3 << SHIFT_MUX | FLAG_MUX), 281 PIN_CONFIG_MUX_FUNC4 = (0x4 << SHIFT_MUX | FLAG_MUX), 282 PIN_CONFIG_MUX_FUNC5 = (0x5 << SHIFT_MUX | FLAG_MUX), 283 PIN_CONFIG_MUX_FUNC6 = (0x6 << SHIFT_MUX | FLAG_MUX), 284 PIN_CONFIG_MUX_FUNC7 = (0x7 << SHIFT_MUX | FLAG_MUX), 285 PIN_CONFIG_MUX_FUNC8 = (0x8 << SHIFT_MUX | FLAG_MUX), 286 PIN_CONFIG_MUX_FUNC9 = (0x9 << SHIFT_MUX | FLAG_MUX), 287 PIN_CONFIG_MUX_FUNC10 = (0xa << SHIFT_MUX | FLAG_MUX), 288 PIN_CONFIG_MUX_FUNC11 = (0xb << SHIFT_MUX | FLAG_MUX), 289 PIN_CONFIG_MUX_FUNC12 = (0xc << SHIFT_MUX | FLAG_MUX), 290 PIN_CONFIG_MUX_FUNC13 = (0xd << SHIFT_MUX | FLAG_MUX), 291 PIN_CONFIG_MUX_FUNC14 = (0xe << SHIFT_MUX | FLAG_MUX), 292 PIN_CONFIG_MUX_FUNC15 = (0xf << SHIFT_MUX | FLAG_MUX), 293 PIN_CONFIG_MUX_DEFAULT = PIN_CONFIG_MUX_FUNC0, 294 295 #if defined(SOC_SWALLOW) 296 PIN_CONFIG_PUL_NORMAL = (0x1 << SHIFT_PUL | FLAG_PUL), 297 PIN_CONFIG_PUL_DEFAULT = (0x0 << SHIFT_PUL | FLAG_PUL), 298 PIN_CONFIG_PUL_UP = PIN_CONFIG_PUL_DEFAULT, 299 PIN_CONFIG_PUL_DOWN = PIN_CONFIG_PUL_DEFAULT, 300 PIN_CONFIG_PUL_KEEP = PIN_CONFIG_PUL_DEFAULT, 301 #else 302 PIN_CONFIG_PUL_NORMAL = (0x0 << SHIFT_PUL | FLAG_PUL), 303 PIN_CONFIG_PUL_UP = (0x1 << SHIFT_PUL | FLAG_PUL), 304 PIN_CONFIG_PUL_DOWN = (0x2 << SHIFT_PUL | FLAG_PUL), 305 PIN_CONFIG_PUL_KEEP = (0x3 << SHIFT_PUL | FLAG_PUL), 306 PIN_CONFIG_PUL_DEFAULT = PIN_CONFIG_PUL_NORMAL, 307 #endif 308 309 #if defined(SOC_RK3568) 310 PIN_CONFIG_DRV_LEVEL0 = (0x1 << SHIFT_DRV | FLAG_DRV), 311 PIN_CONFIG_DRV_LEVEL1 = (0x3 << SHIFT_DRV | FLAG_DRV), 312 PIN_CONFIG_DRV_LEVEL2 = (0x7 << SHIFT_DRV | FLAG_DRV), 313 PIN_CONFIG_DRV_LEVEL3 = (0xf << SHIFT_DRV | FLAG_DRV), 314 PIN_CONFIG_DRV_LEVEL4 = (0x1f << SHIFT_DRV | FLAG_DRV), 315 PIN_CONFIG_DRV_LEVEL5 = (0x3f << SHIFT_DRV | FLAG_DRV), 316 PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2, 317 #else 318 PIN_CONFIG_DRV_LEVEL0 = (0x0 << SHIFT_DRV | FLAG_DRV), 319 PIN_CONFIG_DRV_LEVEL1 = (0x1 << SHIFT_DRV | FLAG_DRV), 320 PIN_CONFIG_DRV_LEVEL2 = (0x2 << SHIFT_DRV | FLAG_DRV), 321 PIN_CONFIG_DRV_LEVEL3 = (0x3 << SHIFT_DRV | FLAG_DRV), 322 PIN_CONFIG_DRV_LEVEL4 = (0x4 << SHIFT_DRV | FLAG_DRV), 323 PIN_CONFIG_DRV_LEVEL5 = (0x5 << SHIFT_DRV | FLAG_DRV), 324 PIN_CONFIG_DRV_LEVEL6 = (0x6 << SHIFT_DRV | FLAG_DRV), 325 PIN_CONFIG_DRV_LEVEL7 = (0x7 << SHIFT_DRV | FLAG_DRV), 326 PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2, 327 #endif 328 329 PIN_CONFIG_SRT_SLOW = (0x0 << SHIFT_SRT | FLAG_SRT), 330 PIN_CONFIG_SRT_FAST = (0x1 << SHIFT_SRT | FLAG_SRT), 331 PIN_CONFIG_SRT_DEFAULT = PIN_CONFIG_SRT_SLOW, 332 333 PIN_CONFIG_SMT_DISABLE = (0x0 << SHIFT_SMT | FLAG_SMT), 334 PIN_CONFIG_SMT_ENABLE = (0x1 << SHIFT_SMT | FLAG_SMT), 335 PIN_CONFIG_SMT_DEFAULT = PIN_CONFIG_SMT_DISABLE, 336 337 PIN_CONFIG_MAX = 0xFFFFFFFFU, 338 } ePINCTRL_configParam; 339 340 typedef enum { 341 GRF_MUX_INFO = 0, 342 GRF_PUL_INFO, 343 GRF_DRV_INFO, 344 GRF_SRT_INFO, 345 GRF_SMT_INFO, 346 GRF_INFO_NUM 347 } ePIN_GRF_INFO_ID; 348 349 #define PIN_BANK_CFG_FLAGS(chn, cnt, reg, \ 350 offset0, bpp0, ppr0, \ 351 offset1, bpp1, ppr1, \ 352 offset2, bpp2, ppr2, \ 353 offset3, bpp3, ppr3, \ 354 offset4, bpp4, ppr4) \ 355 { \ 356 .channel = chn, \ 357 .pinCount = cnt, \ 358 .grfBase = reg, \ 359 .GRFInfo[GRF_MUX_INFO] = { .offset = offset0, .bitsPerPin = bpp0, .pinsPerReg = ppr0 }, \ 360 .GRFInfo[GRF_PUL_INFO] = { .offset = offset1, .bitsPerPin = bpp1, .pinsPerReg = ppr1 }, \ 361 .GRFInfo[GRF_DRV_INFO] = { .offset = offset2, .bitsPerPin = bpp2, .pinsPerReg = ppr2 }, \ 362 .GRFInfo[GRF_SRT_INFO] = { .offset = offset3, .bitsPerPin = bpp3, .pinsPerReg = ppr3 }, \ 363 .GRFInfo[GRF_SMT_INFO] = { .offset = offset4, .bitsPerPin = bpp4, .pinsPerReg = ppr4 }, \ 364 } 365 366 /** @defgroup ePINCTRL_GPIO_PINS Pins Definition 367 * @{ 368 */ 369 typedef enum { 370 GPIO_PIN_A0 = 0x00000001U, /*!< Pin 0 selected */ 371 GPIO_PIN_A1 = 0x00000002U, /*!< Pin 1 selected */ 372 GPIO_PIN_A2 = 0x00000004U, /*!< Pin 2 selected */ 373 GPIO_PIN_A3 = 0x00000008U, /*!< Pin 3 selected */ 374 GPIO_PIN_A4 = 0x00000010U, /*!< Pin 4 selected */ 375 GPIO_PIN_A5 = 0x00000020U, /*!< Pin 5 selected */ 376 GPIO_PIN_A6 = 0x00000040U, /*!< Pin 6 selected */ 377 GPIO_PIN_A7 = 0x00000080U, /*!< Pin 7 selected */ 378 GPIO_PIN_B0 = 0x00000100U, /*!< Pin 8 selected */ 379 GPIO_PIN_B1 = 0x00000200U, /*!< Pin 9 selected */ 380 GPIO_PIN_B2 = 0x00000400U, /*!< Pin 10 selected */ 381 GPIO_PIN_B3 = 0x00000800U, /*!< Pin 11 selected */ 382 GPIO_PIN_B4 = 0x00001000U, /*!< Pin 12 selected */ 383 GPIO_PIN_B5 = 0x00002000U, /*!< Pin 13 selected */ 384 GPIO_PIN_B6 = 0x00004000U, /*!< Pin 14 selected */ 385 GPIO_PIN_B7 = 0x00008000U, /*!< Pin 15 selected */ 386 GPIO_PIN_C0 = 0x00010000U, /*!< Pin 16 selected */ 387 GPIO_PIN_C1 = 0x00020000U, /*!< Pin 17 selected */ 388 GPIO_PIN_C2 = 0x00040000U, /*!< Pin 18 selected */ 389 GPIO_PIN_C3 = 0x00080000U, /*!< Pin 19 selected */ 390 GPIO_PIN_C4 = 0x00100000U, /*!< Pin 20 selected */ 391 GPIO_PIN_C5 = 0x00200000U, /*!< Pin 21 selected */ 392 GPIO_PIN_C6 = 0x00400000U, /*!< Pin 22 selected */ 393 GPIO_PIN_C7 = 0x00800000U, /*!< Pin 23 selected */ 394 GPIO_PIN_D0 = 0x01000000U, /*!< Pin 24 selected */ 395 GPIO_PIN_D1 = 0x02000000U, /*!< Pin 25 selected */ 396 GPIO_PIN_D2 = 0x04000000U, /*!< Pin 26 selected */ 397 GPIO_PIN_D3 = 0x08000000U, /*!< Pin 27 selected */ 398 GPIO_PIN_D4 = 0x10000000U, /*!< Pin 28 selected */ 399 GPIO_PIN_D5 = 0x20000000U, /*!< Pin 29 selected */ 400 GPIO_PIN_D6 = 0x40000000U, /*!< Pin 30 selected */ 401 GPIO_PIN_D7 = 0x80000000U, /*!< Pin 31 selected */ 402 } ePINCTRL_GPIO_PINS; 403 404 #define GPIO_PIN_ALL (0xFFFFFFFFU) /*!< All pins selected */ 405 406 /** @} */ 407 408 #define ROUTE_VAL(v, s, m) (((v) << (s)) | (m) << ((s) + 16)) 409 410 /***************************** Structure Definition **************************/ 411 412 struct PINCTRL_GRF_INFO { 413 uint16_t offset; 414 uint8_t bitsPerPin; 415 uint8_t pinsPerReg; 416 }; 417 418 struct PINCTRL_MUX_RECAL_DATA { 419 uint32_t reg; 420 uint8_t bank; 421 uint8_t pin; 422 uint8_t bit; 423 uint8_t mask; 424 }; 425 426 struct PINCTRL_MUX_ROUTE_DATA { 427 uint32_t routeReg; 428 uint32_t routeVal; 429 uint32_t pin; 430 uint8_t bank; 431 uint8_t func; 432 }; 433 434 struct PINCTRL_BANK_INFO { 435 struct PINCTRL_GRF_INFO GRFInfo[GRF_INFO_NUM]; 436 uint32_t grfBase; 437 uint8_t pinCount; 438 uint8_t channel; 439 }; 440 441 struct HAL_PINCTRL_DEV { 442 const struct PINCTRL_BANK_INFO *banks; 443 const struct PINCTRL_MUX_RECAL_DATA *muxRecalData; 444 const struct PINCTRL_MUX_ROUTE_DATA *muxRouteData; 445 uint8_t banksNum; 446 uint8_t muxRecalDataNum; 447 uint8_t muxRouteDataNum; 448 }; 449 450 /** @brief Rockchip pinctrl device struct define 451 * Define a struct for pinctrl, including banks info, bank number, 452 * and grf info about iomux offset, iomux bit info, drive/pull/ 453 * slewrate/schmitt offset and bit info. 454 */ 455 extern const struct HAL_PINCTRL_DEV g_pinDev; 456 457 /** @} */ 458 459 /***************************** Function Declare ******************************/ 460 /** @defgroup PINCTRL_Public_Function_Declare Public Function Declare 461 * @{ 462 */ 463 464 HAL_Status HAL_PINCTRL_Suspend(void); 465 HAL_Status HAL_PINCTRL_Resume(void); 466 467 HAL_Status HAL_PINCTRL_Init(void); 468 HAL_Status HAL_PINCTRL_DeInit(void); 469 470 HAL_Status HAL_PINCTRL_SetParam(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param); 471 HAL_Status HAL_PINCTRL_SetIOMUX(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param); 472 473 HAL_Status HAL_PINCTRL_IOFuncSelForCIF(eIOFUNC_SEL mode); 474 HAL_Status HAL_PINCTRL_IOFuncSelForEMMC(eIOFUNC_SEL mode); 475 HAL_Status HAL_PINCTRL_IOFuncSelForFLASH(eIOFUNC_SEL mode); 476 HAL_Status HAL_PINCTRL_IOFuncSelForFSPI(eIOFUNC_SEL mode); 477 HAL_Status HAL_PINCTRL_IOFuncSelForLCDC(eIOFUNC_SEL mode); 478 HAL_Status HAL_PINCTRL_IOFuncSelForMIPICSI(eIOFUNC_SEL mode); 479 HAL_Status HAL_PINCTRL_IOFuncSelForRGMII(eIOFUNC_SEL mode); 480 HAL_Status HAL_PINCTRL_IOFuncSelForGMAC0(eIOFUNC_SEL mode); 481 HAL_Status HAL_PINCTRL_IOFuncSelForGMAC1(eIOFUNC_SEL mode); 482 HAL_Status HAL_PINCTRL_IOFuncSelForSDIO(eIOFUNC_SEL mode); 483 HAL_Status HAL_PINCTRL_IOFuncSelForSDMMC0(eIOFUNC_SEL mode); 484 485 HAL_Status HAL_PINCTRL_IOFuncSelForCAN0(eIOFUNC_SEL mode); 486 HAL_Status HAL_PINCTRL_IOFuncSelForCAN1(eIOFUNC_SEL mode); 487 HAL_Status HAL_PINCTRL_IOFuncSelForCAN2(eIOFUNC_SEL mode); 488 HAL_Status HAL_PINCTRL_IOFuncSelForCAN3(eIOFUNC_SEL mode); 489 HAL_Status HAL_PINCTRL_IOFuncSelForCAN4(eIOFUNC_SEL mode); 490 HAL_Status HAL_PINCTRL_IOFuncSelForCAN5(eIOFUNC_SEL mode); 491 HAL_Status HAL_PINCTRL_IOFuncSelForI2C0(eIOFUNC_SEL mode); 492 HAL_Status HAL_PINCTRL_IOFuncSelForI2C1(eIOFUNC_SEL mode); 493 HAL_Status HAL_PINCTRL_IOFuncSelForI2C2(eIOFUNC_SEL mode); 494 HAL_Status HAL_PINCTRL_IOFuncSelForI2C3(eIOFUNC_SEL mode); 495 HAL_Status HAL_PINCTRL_IOFuncSelForI2C4(eIOFUNC_SEL mode); 496 HAL_Status HAL_PINCTRL_IOFuncSelForI2C5(eIOFUNC_SEL mode); 497 HAL_Status HAL_PINCTRL_IOFuncSelForI2S0(eIOFUNC_SEL mode); 498 HAL_Status HAL_PINCTRL_IOFuncSelForI2S1(eIOFUNC_SEL mode); 499 HAL_Status HAL_PINCTRL_IOFuncSelForI2S2(eIOFUNC_SEL mode); 500 HAL_Status HAL_PINCTRL_IOFuncSelForPWM0(eIOFUNC_SEL mode); 501 HAL_Status HAL_PINCTRL_IOFuncSelForPWM1(eIOFUNC_SEL mode); 502 HAL_Status HAL_PINCTRL_IOFuncSelForPWM2(eIOFUNC_SEL mode); 503 HAL_Status HAL_PINCTRL_IOFuncSelForPWM3(eIOFUNC_SEL mode); 504 HAL_Status HAL_PINCTRL_IOFuncSelForPWM4(eIOFUNC_SEL mode); 505 HAL_Status HAL_PINCTRL_IOFuncSelForPWM5(eIOFUNC_SEL mode); 506 HAL_Status HAL_PINCTRL_IOFuncSelForPWM6(eIOFUNC_SEL mode); 507 HAL_Status HAL_PINCTRL_IOFuncSelForPWM7(eIOFUNC_SEL mode); 508 HAL_Status HAL_PINCTRL_IOFuncSelForPWM8(eIOFUNC_SEL mode); 509 HAL_Status HAL_PINCTRL_IOFuncSelForPWM9(eIOFUNC_SEL mode); 510 HAL_Status HAL_PINCTRL_IOFuncSelForPWM10(eIOFUNC_SEL mode); 511 HAL_Status HAL_PINCTRL_IOFuncSelForPWM11(eIOFUNC_SEL mode); 512 HAL_Status HAL_PINCTRL_IOFuncSelForSPI0(eIOFUNC_SEL mode); 513 HAL_Status HAL_PINCTRL_IOFuncSelForSPI1(eIOFUNC_SEL mode); 514 HAL_Status HAL_PINCTRL_IOFuncSelForSPI2(eIOFUNC_SEL mode); 515 HAL_Status HAL_PINCTRL_IOFuncSelForSPI3(eIOFUNC_SEL mode); 516 HAL_Status HAL_PINCTRL_IOFuncSelForSPI4(eIOFUNC_SEL mode); 517 HAL_Status HAL_PINCTRL_IOFuncSelForSPI5(eIOFUNC_SEL mode); 518 HAL_Status HAL_PINCTRL_IOFuncSelForUART0(eIOFUNC_SEL mode); 519 HAL_Status HAL_PINCTRL_IOFuncSelForUART1(eIOFUNC_SEL mode); 520 HAL_Status HAL_PINCTRL_IOFuncSelForUART2(eIOFUNC_SEL mode); 521 HAL_Status HAL_PINCTRL_IOFuncSelForUART3(eIOFUNC_SEL mode); 522 HAL_Status HAL_PINCTRL_IOFuncSelForUART4(eIOFUNC_SEL mode); 523 HAL_Status HAL_PINCTRL_IOFuncSelForUART5(eIOFUNC_SEL mode); 524 HAL_Status HAL_PINCTRL_IOFuncSelForUART6(eIOFUNC_SEL mode); 525 HAL_Status HAL_PINCTRL_IOFuncSelForUART7(eIOFUNC_SEL mode); 526 HAL_Status HAL_PINCTRL_IOFuncSelForUART8(eIOFUNC_SEL mode); 527 HAL_Status HAL_PINCTRL_IOFuncSelForUART9(eIOFUNC_SEL mode); 528 HAL_Status HAL_PINCTRL_IOFuncSelForUART10(eIOFUNC_SEL mode); 529 HAL_Status HAL_PINCTRL_IOFuncSelForUART11(eIOFUNC_SEL mode); 530 531 /** @} */ 532 533 #endif /* __HAL_PINCTRL_H__ */ 534 535 /** @} */ 536 537 /** @} */ 538