1 /*
2 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2021-10-12 Steven Liu first implementation
9 */
10
11 #include "rtdef.h"
12 #include "iomux.h"
13 #include "hal_base.h"
14
15 /**
16 * @brief Config iomux for M4 JTAG
17 */
m4_jtag_iomux_config(void)18 rt_weak void m4_jtag_iomux_config(void)
19 {
20 HAL_PINCTRL_SetIOMUX(GPIO_BANK0,
21 GPIO_PIN_C7 | // M4_JTAG_TCK
22 GPIO_PIN_D0, // M4_JTAG_TMS
23 PIN_CONFIG_MUX_FUNC2);
24 }
25
26 /**
27 * @brief Config iomux for UART0
28 */
uart0_iomux_config(void)29 rt_weak void uart0_iomux_config(void)
30 {
31 HAL_PINCTRL_SetIOMUX(GPIO_BANK0,
32 GPIO_PIN_C7 | // UART0_RX
33 GPIO_PIN_D0, // UART0_TX
34 PIN_CONFIG_MUX_FUNC1);
35 }
36
37 /**
38 * @brief Config iomux for UART1
39 */
uart1_m0_iomux_config(void)40 rt_weak void uart1_m0_iomux_config(void)
41 {
42 HAL_PINCTRL_SetIOMUX(GPIO_BANK0,
43 GPIO_PIN_D1 | // UART1_RX_M0
44 GPIO_PIN_D2, // UART1_TX_M0
45 PIN_CONFIG_MUX_FUNC2);
46
47 WRITE_REG_MASK_WE(GRF->SOC_CON5,
48 GRF_SOC_CON5_GRF_CON_UART1_IOMUX_SEL_MASK,
49 (0 << GRF_SOC_CON5_GRF_CON_UART1_IOMUX_SEL_SHIFT));
50 }
51
uart1_m1_iomux_config(void)52 rt_weak void uart1_m1_iomux_config(void)
53 {
54 HAL_PINCTRL_SetIOMUX(GPIO_BANK0,
55 GPIO_PIN_A5 | // UART1_RX_M1
56 GPIO_PIN_A4, // UART1_TX_M1
57 PIN_CONFIG_MUX_FUNC2);
58
59 WRITE_REG_MASK_WE(GRF->SOC_CON5,
60 GRF_SOC_CON5_GRF_CON_UART1_IOMUX_SEL_MASK,
61 (1 << GRF_SOC_CON5_GRF_CON_UART1_IOMUX_SEL_SHIFT));
62 }
63
uart1_m2_iomux_config(void)64 rt_weak void uart1_m2_iomux_config(void)
65 {
66 HAL_PINCTRL_SetIOMUX(GPIO_BANK1,
67 GPIO_PIN_B1 | // UART1_RX_M2
68 GPIO_PIN_B0, // UART1_TX_M2
69 PIN_CONFIG_MUX_FUNC3);
70
71 WRITE_REG_MASK_WE(GRF->SOC_CON5,
72 GRF_SOC_CON5_GRF_CON_UART1_IOMUX_SEL_MASK,
73 (2 << GRF_SOC_CON5_GRF_CON_UART1_IOMUX_SEL_SHIFT));
74 }
75
uart1_m3_iomux_config(void)76 rt_weak void uart1_m3_iomux_config(void)
77 {
78 HAL_PINCTRL_SetIOMUX(GPIO_BANK0,
79 GPIO_PIN_A5, // UART1_RX_M3
80 PIN_CONFIG_MUX_FUNC2);
81
82 HAL_PINCTRL_SetIOMUX(GPIO_BANK0,
83 GPIO_PIN_B1, // UART1_TX_M3
84 PIN_CONFIG_MUX_FUNC4);
85
86 WRITE_REG_MASK_WE(GRF->SOC_CON5,
87 GRF_SOC_CON5_GRF_CON_UART1_IOMUX_SEL_MASK,
88 (3 << GRF_SOC_CON5_GRF_CON_UART1_IOMUX_SEL_SHIFT));
89 }
90
91 /**
92 * @brief Config iomux for UART2
93 */
uart2_iomux_config(void)94 rt_weak void uart2_iomux_config(void)
95 {
96 HAL_PINCTRL_SetIOMUX(GPIO_BANK1,
97 GPIO_PIN_A0 | // UART2_RX
98 GPIO_PIN_A1 | // UART2_TX
99 GPIO_PIN_A2 | // UART2_CTS
100 GPIO_PIN_A3, // UART2_RTS
101 PIN_CONFIG_MUX_FUNC4);
102 }
103
104 /**
105 * @brief Config iomux for RK2108
106 */
rt_hw_iomux_config(void)107 rt_weak void rt_hw_iomux_config(void)
108 {
109 uart2_iomux_config();
110
111 #ifdef M4_JTAG_ENABLE
112 m4_jtag_iomux_config();
113 #else
114 uart0_iomux_config();
115 #endif
116 }
117