1 /*
2 * Copyright 2017 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
12 * Note: The clock could not be set when it is being used as system clock.
13 * In default out of reset, the CPU is clocked from FIRC(IRC48M),
14 * so before setting FIRC, change to use another avaliable clock source.
15 *
16 * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
17 *
18 * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
19 * Wait until the system clock source is changed to target source.
20 *
21 * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
22 * corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
23 * Supported run mode and clock restrictions could be found in Reference Manual.
24 */
25
26 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
27 !!GlobalInfo
28 product: Clocks v3.0
29 processor: RV32M1
30 package_id: RV32M1
31 mcu_data: ksdk2_0
32 processor_version: 0.0.0
33 board: RV32M1_VEGA
34 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
35
36 #include "fsl_msmc.h"
37 #include "clock_config.h"
38
39 /*******************************************************************************
40 * Definitions
41 ******************************************************************************/
42 #define SCG_LPFLL_DISABLE 0U /*!< LPFLL clock disabled */
43 #define SCG_SOSC_DISABLE 0U /*!< System OSC disabled */
44
45 /*******************************************************************************
46 * Variables
47 ******************************************************************************/
48 /* System clock frequency. */
49 extern uint32_t SystemCoreClock;
50
51 /*******************************************************************************
52 * Code
53 ******************************************************************************/
54 #ifndef SDK_SECONDARY_CORE
55 /*FUNCTION**********************************************************************
56 *
57 * Function Name : CLOCK_CONFIG_FircSafeConfig
58 * Description : This function is used to safely configure FIRC clock.
59 * In default out of reset, the CPU is clocked from FIRC(IRC48M).
60 * Before setting FIRC, change to use SIRC as system clock,
61 * then configure FIRC.
62 * Param fircConfig : FIRC configuration.
63 *
64 *END**************************************************************************/
CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t * fircConfig)65 static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
66 {
67 scg_sys_clk_config_t curConfig;
68 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
69 .div1 = kSCG_AsyncClkDisable,
70 .div2 = kSCG_AsyncClkDivBy2,
71 .range = kSCG_SircRangeHigh};
72 scg_sys_clk_config_t sysClkSafeConfigSource = {
73 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider. */
74 .divCore = kSCG_SysClkDivBy1, /* Core clock divider. */
75 .src = kSCG_SysClkSrcSirc /* System clock source. */
76 };
77 /* Init Sirc */
78 CLOCK_InitSirc(&scgSircConfig);
79 /* Change to use SIRC as system clock source to prepare to change FIRCCFG register */
80 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
81 /* Wait for clock source switch finished */
82 do
83 {
84 CLOCK_GetCurSysClkConfig(&curConfig);
85 } while (curConfig.src != sysClkSafeConfigSource.src);
86
87 /* Init Firc */
88 CLOCK_InitFirc(fircConfig);
89 }
90 #endif
91
92 /*******************************************************************************
93 ************************ BOARD_InitBootClocks function ************************
94 ******************************************************************************/
BOARD_InitBootClocks(void)95 void BOARD_InitBootClocks(void)
96 {
97 BOARD_BootClockRUN();
98 }
99
100 /*******************************************************************************
101 ********************** Configuration BOARD_BootClockRUN ***********************
102 ******************************************************************************/
103 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
104 !!Configuration
105 name: BOARD_BootClockRUN
106 called_from_default_init: true
107 outputs:
108 - {id: Bus_clock.outFreq, value: 48 MHz}
109 - {id: Core_clock.outFreq, value: 48 MHz}
110 - {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
111 - {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
112 - {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
113 - {id: LPO_CLK.outFreq, value: 1 kHz}
114 - {id: Platform_clock.outFreq, value: 48 MHz}
115 - {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
116 - {id: Slow_clock.outFreq, value: 24 MHz}
117 - {id: System_clock.outFreq, value: 48 MHz}
118 settings:
119 - {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
120 - {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
121 - {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
122 - {id: SCG.LPFLLDIV1.scale, value: '1', locked: true}
123 - {id: SCG.LPFLLDIV3.scale, value: '0', locked: true}
124 - {id: SCG.SIRCDIV1.scale, value: '0', locked: true}
125 - {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
126 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
127
128 /*******************************************************************************
129 * Variables for BOARD_BootClockRUN configuration
130 ******************************************************************************/
131 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
132 {
133 .divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
134 .divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
135 .divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
136 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
137 .src = kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */
138 };
139 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
140 {
141 .freq = 0U, /* System Oscillator frequency: 0Hz */
142 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
143 .enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
144 .div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
145 .div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
146 .div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
147 };
148 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
149 {
150 .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
151 .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
152 .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
153 .div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
154 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
155 };
156 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
157 {
158 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
159 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
160 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
161 .div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
162 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
163 .trimConfig = NULL,
164 };
165 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockRUN =
166 {
167 .enableMode = SCG_LPFLL_DISABLE, /* LPFLL clock disabled */
168 .div1 = kSCG_AsyncClkDivBy1, /* Low Power FLL Clock Divider 1: divided by 1 */
169 .div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
170 .div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
171 .range = kSCG_LpFllRange48M, /* LPFLL is trimmed to 48MHz */
172 .trimConfig = NULL,
173 };
174 /*******************************************************************************
175 * Code for BOARD_BootClockRUN configuration
176 ******************************************************************************/
BOARD_BootClockRUN(void)177 void BOARD_BootClockRUN(void)
178 {
179 #ifndef SDK_SECONDARY_CORE
180 scg_sys_clk_config_t curConfig;
181
182 /* Init FIRC */
183 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
184 /* Set SCG to FIRC mode. */
185 CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
186 /* Wait for clock source switch finished */
187 do
188 {
189 CLOCK_GetCurSysClkConfig(&curConfig);
190 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
191 /* Init SIRC */
192 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
193 /* Init LPFLL */
194 CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockRUN);
195 /* Set SystemCoreClock variable. */
196 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
197 #endif
198 }
199
200 /*******************************************************************************
201 ********************* Configuration BOARD_BootClockHSRUN **********************
202 ******************************************************************************/
203 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
204 !!Configuration
205 name: BOARD_BootClockHSRUN
206 outputs:
207 - {id: Bus_clock.outFreq, value: 72 MHz}
208 - {id: Core_clock.outFreq, value: 72 MHz}
209 - {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
210 - {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
211 - {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
212 - {id: LPO_CLK.outFreq, value: 1 kHz}
213 - {id: Platform_clock.outFreq, value: 72 MHz}
214 - {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
215 - {id: Slow_clock.outFreq, value: 8 MHz}
216 - {id: System_clock.outFreq, value: 72 MHz}
217 settings:
218 - {id: SCGMode, value: LPFLL}
219 - {id: powerMode, value: HSRUN}
220 - {id: SCG.DIVCORE.scale, value: '1', locked: true}
221 - {id: SCG.DIVSLOW.scale, value: '9'}
222 - {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
223 - {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
224 - {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
225 - {id: SCG.LPFLLDIV1.scale, value: '0', locked: true}
226 - {id: SCG.LPFLL_mul.scale, value: '36', locked: true}
227 - {id: SCG.SCSSEL.sel, value: SCG.LPFLL}
228 - {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
229 - {id: SCG.TRIMDIV.scale, value: '24'}
230 - {id: SCG.TRIMSRCSEL.sel, value: SCG.FIRC}
231 - {id: 'SCG::RCCR[SCS].bitField', value: '5'}
232 - {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
233 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
234
235 /*******************************************************************************
236 * Variables for BOARD_BootClockHSRUN configuration
237 ******************************************************************************/
238 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN =
239 {
240 .divSlow = kSCG_SysClkDivBy9, /* Slow Clock Divider: divided by 9 */
241 .divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
242 .divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
243 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
244 .src = kSCG_SysClkSrcLpFll, /* Low power FLL is selected as System Clock Source */
245 };
246 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN =
247 {
248 .freq = 0U, /* System Oscillator frequency: 0Hz */
249 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
250 .enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
251 .div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
252 .div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
253 .div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
254 };
255 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN =
256 {
257 .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
258 .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
259 .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
260 .div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
261 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
262 };
263 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN =
264 {
265 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
266 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
267 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
268 .div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
269 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
270 .trimConfig = NULL,
271 };
272 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockHSRUN =
273 {
274 .enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
275 .div1 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 1: Clock output is disabled */
276 .div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
277 .div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
278 .range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */
279 .trimConfig = NULL,
280 };
281 /*******************************************************************************
282 * Code for BOARD_BootClockHSRUN configuration
283 ******************************************************************************/
BOARD_BootClockHSRUN(void)284 void BOARD_BootClockHSRUN(void)
285 {
286 #ifndef SDK_SECONDARY_CORE
287 scg_sys_clk_config_t curConfig;
288
289 /* Init FIRC */
290 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
291 /* Init LPFLL */
292 CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockHSRUN);
293 #if defined(CPU_RV32M1_cm4) || defined(CPU_RV32M1_ri5cy)
294 /* Set HSRUN power mode */
295 SMC_SetPowerModeProtection(SMC0, kSMC_AllowPowerModeAll);
296 SMC_SetPowerModeHsrun(SMC0);
297 while (SMC_GetPowerModeState(SMC0) != kSMC_PowerStateHsrun)
298 {
299 }
300 #elif defined(CPU_RV32M1_cm0plus) || defined(CPU_RV32M1_zero_riscy)
301 SMC_SetPowerModeProtection(SMC1, kSMC_AllowPowerModeAll);
302 SMC_SetPowerModeHsrun(SMC1);
303 while (SMC_GetPowerModeState(SMC1) != kSMC_PowerStateHsrun)
304 {
305 }
306 #endif
307 /* Set SCG to LPFLL mode. */
308 CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
309 /* Wait for clock source switch finished */
310 do
311 {
312 CLOCK_GetCurSysClkConfig(&curConfig);
313 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
314 /* Init SIRC */
315 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
316 /* Set SystemCoreClock variable. */
317 SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
318 #endif
319 }
320
321 /*******************************************************************************
322 ********************* Configuration BOARD_BootClockVLPR ***********************
323 ******************************************************************************/
324 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
325 !!Configuration
326 name: BOARD_BootClockVLPR
327 outputs:
328 - {id: Bus_clock.outFreq, value: 2 MHz}
329 - {id: Core_clock.outFreq, value: 4 MHz}
330 - {id: LPO_CLK.outFreq, value: 1 kHz}
331 - {id: Platform_clock.outFreq, value: 4 MHz}
332 - {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
333 - {id: SIRCDIV2_CLK.outFreq, value: 8 MHz}
334 - {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
335 - {id: Slow_clock.outFreq, value: 4000/9 kHz}
336 - {id: System_clock.outFreq, value: 4 MHz}
337 settings:
338 - {id: SCGMode, value: SIRC}
339 - {id: powerMode, value: VLPR}
340 - {id: SCG.DIVBUS.scale, value: '2', locked: true}
341 - {id: SCG.DIVCORE.scale, value: '2', locked: true}
342 - {id: SCG.DIVSLOW.scale, value: '9'}
343 - {id: SCG.FIRCDIV1.scale, value: '1'}
344 - {id: SCG.SCSSEL.sel, value: SCG.SIRC}
345 - {id: SCG.SIRCDIV1.scale, value: '1', locked: true}
346 - {id: SCG.SIRCDIV2.scale, value: '1', locked: true}
347 - {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
348 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
349
350 /*******************************************************************************
351 * Variables for BOARD_BootClockVLPR configuration
352 ******************************************************************************/
353 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR =
354 {
355 .divSlow = kSCG_SysClkDivBy9, /* Slow Clock Divider: divided by 9 */
356 .divBus = kSCG_SysClkDivBy2, /* Bus Clock Divider: divided by 2 */
357 .divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
358 .divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
359 .src = kSCG_SysClkSrcSirc, /* Slow IRC is selected as System Clock Source */
360 };
361 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR =
362 {
363 .freq = 0U, /* System Oscillator frequency: 0Hz */
364 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
365 .enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
366 .div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
367 .div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
368 .div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
369 };
370 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
371 {
372 .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
373 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
374 .div2 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 2: divided by 1 */
375 .div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
376 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
377 };
378 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR =
379 {
380 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
381 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
382 .div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
383 .div3 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 3: Clock output is disabled */
384 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
385 .trimConfig = NULL,
386 };
387 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockVLPR =
388 {
389 .enableMode = SCG_LPFLL_DISABLE, /* LPFLL clock disabled */
390 .div1 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 1: Clock output is disabled */
391 .div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
392 .div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
393 .range = kSCG_LpFllRange48M, /* LPFLL is trimmed to 48MHz */
394 .trimConfig = NULL,
395 };
396 /*******************************************************************************
397 * Code for BOARD_BootClockVLPR configuration
398 ******************************************************************************/
BOARD_BootClockVLPR(void)399 void BOARD_BootClockVLPR(void)
400 {
401 #ifndef SDK_SECONDARY_CORE
402 scg_sys_clk_config_t curConfig;
403
404 /* Init SIRC */
405 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockVLPR);
406 /* Set SCG to SIRC mode. */
407 CLOCK_SetVlprModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockVLPR);
408 /* Init FIRC */
409 CLOCK_InitFirc(&g_scgFircConfig_BOARD_BootClockVLPR);
410 /* Init LPFLL */
411 CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockVLPR);
412 #if defined(CPU_RV32M1_cm4) || defined(CPU_RV32M1_ri5cy)
413 /* Set VLPR power mode. */
414 SMC_SetPowerModeProtection(SMC0, kSMC_AllowPowerModeAll);
415 SMC_SetPowerModeVlpr(SMC0);
416 while (SMC_GetPowerModeState(SMC0) != kSMC_PowerStateVlpr)
417 {
418 }
419 #elif defined(CPU_RV32M1_cm0plus) || defined(CPU_RV32M1_zero_riscy)
420 /* Set VLPR power mode. */
421 SMC_SetPowerModeProtection(SMC1, kSMC_AllowPowerModeAll);
422 SMC_SetPowerModeVlpr(SMC1);
423 while (SMC_GetPowerModeState(SMC1) != kSMC_PowerStateVlpr)
424 {
425 }
426 #endif
427 /* Wait for clock source switch finished */
428 do
429 {
430 CLOCK_GetCurSysClkConfig(&curConfig);
431 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockVLPR.src);
432 /* Set SystemCoreClock variable. */
433 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
434 #endif
435 }
436
437