1 /*
2 * Copyright 2017 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /*
9 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
10 !!GlobalInfo
11 product: Pins v3.0
12 processor: RV32M1
13 package_id: RV32M1
14 mcu_data: ksdk2_0
15 processor_version: 0.0.0
16 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
17 */
18
19 #include "fsl_common.h"
20 #include "fsl_port.h"
21 #include "pin_mux.h"
22
23 /*FUNCTION**********************************************************************
24 *
25 * Function Name : BOARD_InitBootPins
26 * Description : Calls initialization functions.
27 *
28 *END**************************************************************************/
BOARD_InitBootPins(void)29 void BOARD_InitBootPins(void) {
30 BOARD_InitPins();
31 }
32
33 #define PIN6_IDX 6u /*!< Pin number for pin 6 in a port */
34 #define PIN7_IDX 7u /*!< Pin number for pin 7 in a port */
35 #define PIN8_IDX 8u /*!< Pin number for pin 8 in a port */
36 #define PIN9_IDX 9u /*!< Pin number for pin 9 in a port */
37 #define PIN10_IDX 10u /*!< Pin number for pin 10 in a port */
38 #define PIN11_IDX 11u /*!< Pin number for pin 11 in a port */
39 #define PIN22_IDX 22u /*!< Pin number for pin 22 in a port */
40 #define PIN23_IDX 23u /*!< Pin number for pin 23 in a port */
41 #define PIN24_IDX 24u /*!< Pin number for pin 24 in a port */
42 #define PIN25_IDX 25u /*!< Pin number for pin 25 in a port */
43 #define PIN26_IDX 26u /*!< Pin number for pin 26 in a port */
44 #define PIN27_IDX 27u /*!< Pin number for pin 27 in a port */
45
46 /*
47 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
48 BOARD_InitPins:
49 - options: {callFromInitBoot: 'true', coreID: cm4, enableClock: 'true'}
50 - pin_list:
51 - {pin_num: N2, peripheral: LPUART0, signal: RX, pin_signal: LPCMP0_IN0/PTC7/LLWU_P15/LPSPI0_PCS3/LPUART0_RX/LPI2C1_HREQ/TPM0_CH0/LPTMR1_ALT1}
52 - {pin_num: P3, peripheral: LPUART0, signal: TX, pin_signal: LPCMP0_IN1/PTC8/LPSPI0_SCK/LPUART0_TX/LPI2C0_HREQ/TPM0_CH1}
53 - {pin_num: B5, peripheral: LPUART1, signal: RX, pin_signal: PTA25/LPUART1_RX/LPSPI3_SOUT/LPI2C2_SDAS/FB_AD31}
54 - {pin_num: A5, peripheral: LPUART1, signal: TX, pin_signal: PTA26/LPUART1_TX/LPSPI3_PCS2/LPI2C2_SCLS/FB_AD30}
55 - {pin_num: U11, peripheral: SDHC0, signal: CMD, pin_signal: ADC0_SE12/PTD9/SDHC0_CMD/LPSPI2_SIN/LPI2C1_SCLS/TRACE_DATA0/TPM2_CH2/FXIO0_D29, slew_rate: fast, open_drain: disable,
56 drive_strength: low, pull_select: up, pull_enable: enable}
57 - {pin_num: P10, peripheral: SDHC0, signal: 'DATA, 0', pin_signal: ADC0_SE10/PTD7/SDHC0_D0/LPSPI2_SOUT/EMVSIM0_PD/TRACE_DATA2/TPM2_CH4/FXIO0_D27, slew_rate: fast,
58 open_drain: disable, pull_select: up, pull_enable: enable}
59 - {pin_num: U9, peripheral: SDHC0, signal: 'DATA, 1', pin_signal: ADC0_SE9/PTD6/SDHC0_D1/LPSPI2_SCK/EMVSIM0_IO/TRACE_DATA3/TPM2_CH5/FXIO0_D26, slew_rate: fast,
60 open_drain: disable, pull_select: up, pull_enable: enable}
61 - {pin_num: R11, peripheral: SDHC0, signal: 'DATA, 2', pin_signal: ADC0_SE14/PTD11/SDHC0_D2/USB0_SOF_OUT/LPI2C1_SCL/CLKOUT/TPM2_CH0/FXIO0_D31, slew_rate: fast,
62 open_drain: disable, drive_strength: low, pull_select: up, pull_enable: enable}
63 - {pin_num: P11, peripheral: SDHC0, signal: 'DATA, 3', pin_signal: ADC0_SE13/PTD10/LLWU_P20/SDHC0_D3/LPSPI2_PCS0/LPI2C1_SDA/TRACE_CLK_OUT/TPM2_CH1/FXIO0_D30, slew_rate: fast,
64 open_drain: disable, drive_strength: low, pull_select: up, pull_enable: enable}
65 - {pin_num: T9, peripheral: SDHC0, signal: DCLK, pin_signal: ADC0_SE11/PTD8/LLWU_P19/SDHC0_DCLK/LPSPI2_PCS2/LPI2C1_SDAS/TRACE_DATA1/TPM2_CH3/FXIO0_D28, slew_rate: fast,
66 open_drain: disable, drive_strength: low, pull_select: up, pull_enable: enable}
67 - {pin_num: P6, peripheral: GPIOC, signal: 'GPIO, 27', pin_signal: PTC27/TPM0_CH4, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
68 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
69 */
70
71 /*FUNCTION**********************************************************************
72 *
73 * Function Name : BOARD_InitPins
74 * Description : Configures pin routing and optionally pin electrical features.
75 *
76 *END**************************************************************************/
BOARD_InitPins(void)77 void BOARD_InitPins(void) {
78 CLOCK_EnableClock(kCLOCK_PortA); /* Clock Gate Control: 0x01u */
79 CLOCK_EnableClock(kCLOCK_PortC); /* Clock Gate Control: 0x01u */
80 CLOCK_EnableClock(kCLOCK_PortD); /* Clock Gate Control: 0x01u */
81
82 const port_pin_config_t portc27_pinP6_config = {
83 kPORT_PullDisable, /* Internal pull-up/down resistor is disabled */
84 kPORT_FastSlewRate, /* Fast slew rate is configured */
85 kPORT_PassiveFilterDisable, /* Passive filter is disabled */
86 kPORT_OpenDrainDisable, /* Open drain is disabled */
87 kPORT_LowDriveStrength, /* Low drive strength is configured */
88 kPORT_MuxAsGpio, /* Pin is configured as PTC27 */
89 kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
90 };
91 PORT_SetPinConfig(PORTC, PIN27_IDX, &portc27_pinP6_config); /* PORTC27 (pin P6) is configured as PTC27 */
92 PORT_SetPinMux(PORTC, PIN7_IDX, kPORT_MuxAlt3); /* PORTC7 (pin N2) is configured as LPUART0_RX */
93 PORT_SetPinMux(PORTC, PIN8_IDX, kPORT_MuxAlt3); /* PORTC8 (pin P3) is configured as LPUART0_TX */
94
95 const port_pin_config_t portd10_pinP11_config = {
96 kPORT_PullUp, /* Internal pull-up resistor is enabled */
97 kPORT_FastSlewRate, /* Fast slew rate is configured */
98 kPORT_PassiveFilterDisable, /* Passive filter is disabled */
99 kPORT_OpenDrainDisable, /* Open drain is disabled */
100 kPORT_LowDriveStrength, /* Low drive strength is configured */
101 kPORT_MuxAlt2, /* Pin is configured as SDHC0_D3 */
102 kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
103 };
104 PORT_SetPinConfig(PORTD, PIN10_IDX, &portd10_pinP11_config); /* PORTD10 (pin P11) is configured as SDHC0_D3 */
105 const port_pin_config_t portd11_pinR11_config = {
106 kPORT_PullUp, /* Internal pull-up resistor is enabled */
107 kPORT_FastSlewRate, /* Fast slew rate is configured */
108 kPORT_PassiveFilterDisable, /* Passive filter is disabled */
109 kPORT_OpenDrainDisable, /* Open drain is disabled */
110 kPORT_LowDriveStrength, /* Low drive strength is configured */
111 kPORT_MuxAlt2, /* Pin is configured as SDHC0_D2 */
112 kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
113 };
114 PORT_SetPinConfig(PORTD, PIN11_IDX, &portd11_pinR11_config); /* PORTD11 (pin R11) is configured as SDHC0_D2 */
115 const port_pin_config_t portd6_pinU9_config = {
116 kPORT_PullUp, /* Internal pull-up resistor is enabled */
117 kPORT_FastSlewRate, /* Fast slew rate is configured */
118 kPORT_PassiveFilterDisable, /* Passive filter is disabled */
119 kPORT_OpenDrainDisable, /* Open drain is disabled */
120 kPORT_LowDriveStrength, /* Low drive strength is configured */
121 kPORT_MuxAlt2, /* Pin is configured as SDHC0_D1 */
122 kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
123 };
124 PORT_SetPinConfig(PORTD, PIN6_IDX, &portd6_pinU9_config); /* PORTD6 (pin U9) is configured as SDHC0_D1 */
125 const port_pin_config_t portd7_pinP10_config = {
126 kPORT_PullUp, /* Internal pull-up resistor is enabled */
127 kPORT_FastSlewRate, /* Fast slew rate is configured */
128 kPORT_PassiveFilterDisable, /* Passive filter is disabled */
129 kPORT_OpenDrainDisable, /* Open drain is disabled */
130 kPORT_LowDriveStrength, /* Low drive strength is configured */
131 kPORT_MuxAlt2, /* Pin is configured as SDHC0_D0 */
132 kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
133 };
134 PORT_SetPinConfig(PORTD, PIN7_IDX, &portd7_pinP10_config); /* PORTD7 (pin P10) is configured as SDHC0_D0 */
135 const port_pin_config_t portd8_pinT9_config = {
136 kPORT_PullUp, /* Internal pull-up resistor is enabled */
137 kPORT_FastSlewRate, /* Fast slew rate is configured */
138 kPORT_PassiveFilterDisable, /* Passive filter is disabled */
139 kPORT_OpenDrainDisable, /* Open drain is disabled */
140 kPORT_LowDriveStrength, /* Low drive strength is configured */
141 kPORT_MuxAlt2, /* Pin is configured as SDHC0_DCLK */
142 kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
143 };
144 PORT_SetPinConfig(PORTD, PIN8_IDX, &portd8_pinT9_config); /* PORTD8 (pin T9) is configured as SDHC0_DCLK */
145 const port_pin_config_t portd9_pinU11_config = {
146 kPORT_PullUp, /* Internal pull-up resistor is enabled */
147 kPORT_FastSlewRate, /* Fast slew rate is configured */
148 kPORT_PassiveFilterDisable, /* Passive filter is disabled */
149 kPORT_OpenDrainDisable, /* Open drain is disabled */
150 kPORT_LowDriveStrength, /* Low drive strength is configured */
151 kPORT_MuxAlt2, /* Pin is configured as SDHC0_CMD */
152 kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
153 };
154 PORT_SetPinConfig(PORTD, PIN9_IDX, &portd9_pinU11_config); /* PORTD9 (pin U11) is configured as SDHC0_CMD */
155
156 PORT_SetPinMux(PORTA, PIN22_IDX, kPORT_MuxAsGpio); /* PORTA22 (pin D6) is configured as PTA24 */
157 PORT_SetPinMux(PORTA, PIN23_IDX, kPORT_MuxAsGpio); /* PORTA23 (pin D6) is configured as PTA24 */
158 PORT_SetPinMux(PORTA, PIN24_IDX, kPORT_MuxAsGpio); /* PORTA24 (pin D6) is configured as PTA24 */
159 PORT_SetPinMux(PORTA, PIN25_IDX, kPORT_MuxAlt2); /* PORTA25 (pin B5) is configured as LPUART1_RX */
160 PORT_SetPinMux(PORTA, PIN26_IDX, kPORT_MuxAlt2); /* PORTA26 (pin A5) is configured as LPUART1_TX */
161 }
162
163 /*******************************************************************************
164 * EOF
165 ******************************************************************************/
166