1 /*
2 * Copyright (c) 2006-2023, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2018-03-13 Liuguang the first version.
9 * 2018-03-19 Liuguang add GPIO interrupt mode support.
10 */
11 #include <rtthread.h>
12 #include <rtdevice.h>
13
14 #include "drv_gpio.h"
15
16 #include "fsl_common.h"
17 #include "fsl_gpio.h"
18 #include "fsl_port.h"
19
20 #ifdef RT_USING_PIN
21
22 struct vega_pin
23 {
24 rt_uint16_t pin;
25 GPIO_Type *gpio;
26 rt_uint32_t gpio_pin;
27 };
28
29 struct vega_irq
30 {
31 rt_uint16_t enable;
32 struct rt_pin_irq_hdr irq_info;
33 };
34
35 #define __ARRAY_LEN(array) (sizeof(array)/sizeof(array[0]))
36 #define __VEGA_PIN_DEFAULT {0, 0, 0}
37 #define __VEGA_PIN(INDEX, PORT, PIN) {INDEX, PORT, PIN}
38
39 static const struct vega_pin vega_pin_map[] =
40 {
41 __VEGA_PIN_DEFAULT,
42
43 /* GPIOA */
44 __VEGA_PIN(1, GPIOA, 0),
45 __VEGA_PIN(2, GPIOA, 1),
46 __VEGA_PIN(3, GPIOA, 2),
47 __VEGA_PIN(4, GPIOA, 3),
48 __VEGA_PIN(5, GPIOA, 4),
49 __VEGA_PIN(6, GPIOA, 5),
50 __VEGA_PIN(7, GPIOA, 6),
51 __VEGA_PIN(8, GPIOA, 7),
52 __VEGA_PIN(9, GPIOA, 8),
53 __VEGA_PIN(10, GPIOA, 9),
54 __VEGA_PIN(11, GPIOA, 10),
55 __VEGA_PIN(12, GPIOA, 11),
56 __VEGA_PIN(13, GPIOA, 12),
57 __VEGA_PIN(14, GPIOA, 13),
58 __VEGA_PIN(15, GPIOA, 14),
59 __VEGA_PIN(16, GPIOA, 15),
60 __VEGA_PIN(17, GPIOA, 16),
61 __VEGA_PIN(18, GPIOA, 17),
62 __VEGA_PIN(19, GPIOA, 18),
63 __VEGA_PIN(20, GPIOA, 19),
64 __VEGA_PIN(21, GPIOA, 20),
65 __VEGA_PIN(22, GPIOA, 21),
66 __VEGA_PIN(23, GPIOA, 22),
67 __VEGA_PIN(24, GPIOA, 23),
68 __VEGA_PIN(25, GPIOA, 24),
69 __VEGA_PIN(26, GPIOA, 25),
70 __VEGA_PIN(27, GPIOA, 26),
71 __VEGA_PIN(28, GPIOA, 27),
72 __VEGA_PIN(29, GPIOA, 28),
73 __VEGA_PIN(30, GPIOA, 29),
74 __VEGA_PIN(31, GPIOA, 30),
75 __VEGA_PIN(32, GPIOA, 31),
76
77 /* GPIOB */
78 __VEGA_PIN(33, GPIOB, 0),
79 __VEGA_PIN(34, GPIOB, 1),
80 __VEGA_PIN(35, GPIOB, 2),
81 __VEGA_PIN(36, GPIOB, 3),
82 __VEGA_PIN(37, GPIOB, 4),
83 __VEGA_PIN(38, GPIOB, 5),
84 __VEGA_PIN(39, GPIOB, 6),
85 __VEGA_PIN(40, GPIOB, 7),
86 __VEGA_PIN(41, GPIOB, 8),
87 __VEGA_PIN(42, GPIOB, 9),
88 __VEGA_PIN(43, GPIOB, 10),
89 __VEGA_PIN(44, GPIOB, 11),
90 __VEGA_PIN(45, GPIOB, 12),
91 __VEGA_PIN(46, GPIOB, 13),
92 __VEGA_PIN(47, GPIOB, 14),
93 __VEGA_PIN(48, GPIOB, 15),
94 __VEGA_PIN(49, GPIOB, 16),
95 __VEGA_PIN(50, GPIOB, 17),
96 __VEGA_PIN(51, GPIOB, 18),
97 __VEGA_PIN(52, GPIOB, 19),
98 __VEGA_PIN(53, GPIOB, 20),
99 __VEGA_PIN(54, GPIOB, 21),
100 __VEGA_PIN(55, GPIOB, 22),
101 __VEGA_PIN(56, GPIOB, 23),
102 __VEGA_PIN(57, GPIOB, 24),
103 __VEGA_PIN(58, GPIOB, 25),
104 __VEGA_PIN(59, GPIOB, 26),
105 __VEGA_PIN(60, GPIOB, 27),
106 __VEGA_PIN(61, GPIOB, 28),
107 __VEGA_PIN(62, GPIOB, 29),
108 __VEGA_PIN(63, GPIOB, 30),
109 __VEGA_PIN(64, GPIOB, 31),
110
111 /* GPIOC */
112 __VEGA_PIN(65, GPIOC, 0),
113 __VEGA_PIN(66, GPIOC, 1),
114 __VEGA_PIN(67, GPIOC, 2),
115 __VEGA_PIN(68, GPIOC, 3),
116 __VEGA_PIN(69, GPIOC, 4),
117 __VEGA_PIN(70, GPIOC, 5),
118 __VEGA_PIN(71, GPIOC, 6),
119 __VEGA_PIN(72, GPIOC, 7),
120 __VEGA_PIN(73, GPIOC, 8),
121 __VEGA_PIN(74, GPIOC, 9),
122 __VEGA_PIN(75, GPIOC, 10),
123 __VEGA_PIN(76, GPIOC, 11),
124 __VEGA_PIN(77, GPIOC, 12),
125 __VEGA_PIN(78, GPIOC, 13),
126 __VEGA_PIN(79, GPIOC, 14),
127 __VEGA_PIN(80, GPIOC, 15),
128 __VEGA_PIN(81, GPIOC, 16),
129 __VEGA_PIN(82, GPIOC, 17),
130 __VEGA_PIN(83, GPIOC, 18),
131 __VEGA_PIN(84, GPIOC, 19),
132 __VEGA_PIN(85, GPIOC, 20),
133 __VEGA_PIN(86, GPIOC, 21),
134 __VEGA_PIN(87, GPIOC, 22),
135 __VEGA_PIN(88, GPIOC, 23),
136 __VEGA_PIN(89, GPIOC, 24),
137 __VEGA_PIN(90, GPIOC, 25),
138 __VEGA_PIN(91, GPIOC, 26),
139 __VEGA_PIN(92, GPIOC, 27),
140 __VEGA_PIN(93, GPIOC, 28),
141 __VEGA_PIN(94, GPIOC, 29),
142 __VEGA_PIN(95, GPIOC, 30),
143 __VEGA_PIN(96, GPIOC, 31),
144
145 /* GPIOD */
146 __VEGA_PIN(97, GPIOD, 0),
147 __VEGA_PIN(98, GPIOD, 1),
148 __VEGA_PIN(99, GPIOD, 2),
149 __VEGA_PIN(100, GPIOD, 3),
150 __VEGA_PIN(101, GPIOD, 4),
151 __VEGA_PIN(102, GPIOD, 5),
152 __VEGA_PIN(103, GPIOD, 6),
153 __VEGA_PIN(104, GPIOD, 7),
154 __VEGA_PIN(105, GPIOD, 8),
155 __VEGA_PIN(106, GPIOD, 9),
156 __VEGA_PIN(107, GPIOD, 10),
157 __VEGA_PIN(108, GPIOD, 11),
158 __VEGA_PIN(109, GPIOD, 12),
159 __VEGA_PIN(110, GPIOD, 13),
160 __VEGA_PIN(111, GPIOD, 14),
161 __VEGA_PIN(112, GPIOD, 15),
162 __VEGA_PIN(113, GPIOD, 16),
163 __VEGA_PIN(114, GPIOD, 17),
164 __VEGA_PIN(115, GPIOD, 18),
165 __VEGA_PIN(116, GPIOD, 19),
166 __VEGA_PIN(117, GPIOD, 20),
167 __VEGA_PIN(118, GPIOD, 21),
168 __VEGA_PIN(119, GPIOD, 22),
169 __VEGA_PIN(120, GPIOD, 23),
170 __VEGA_PIN(121, GPIOD, 24),
171 __VEGA_PIN(122, GPIOD, 25),
172 __VEGA_PIN(123, GPIOD, 26),
173 __VEGA_PIN(124, GPIOD, 27),
174 __VEGA_PIN(125, GPIOD, 28),
175 __VEGA_PIN(126, GPIOD, 29),
176 __VEGA_PIN(127, GPIOD, 30),
177 __VEGA_PIN(128, GPIOD, 31),
178
179 /* GPIOE */
180 __VEGA_PIN(129, GPIOE, 0),
181 __VEGA_PIN(130, GPIOE, 1),
182 __VEGA_PIN(131, GPIOE, 2),
183 __VEGA_PIN(132, GPIOE, 3),
184 __VEGA_PIN(133, GPIOE, 4),
185 __VEGA_PIN(134, GPIOE, 5),
186 __VEGA_PIN(135, GPIOE, 6),
187 __VEGA_PIN(136, GPIOE, 7),
188 __VEGA_PIN(137, GPIOE, 8),
189 __VEGA_PIN(138, GPIOE, 9),
190 __VEGA_PIN(139, GPIOE, 10),
191 __VEGA_PIN(140, GPIOE, 11),
192 __VEGA_PIN(141, GPIOE, 12),
193 __VEGA_PIN(142, GPIOE, 13),
194 __VEGA_PIN(143, GPIOE, 14),
195 __VEGA_PIN(144, GPIOE, 15),
196 __VEGA_PIN(145, GPIOE, 16),
197 __VEGA_PIN(146, GPIOE, 17),
198 __VEGA_PIN(147, GPIOE, 18),
199 __VEGA_PIN(148, GPIOE, 19),
200 __VEGA_PIN(149, GPIOE, 20),
201 __VEGA_PIN(150, GPIOE, 21),
202 __VEGA_PIN(151, GPIOE, 22),
203 __VEGA_PIN(152, GPIOE, 23),
204 __VEGA_PIN(153, GPIOE, 24),
205 __VEGA_PIN(154, GPIOE, 25),
206 __VEGA_PIN(155, GPIOE, 26),
207 __VEGA_PIN(156, GPIOE, 27),
208 __VEGA_PIN(157, GPIOE, 28),
209 __VEGA_PIN(158, GPIOE, 29),
210 __VEGA_PIN(159, GPIOE, 30),
211 __VEGA_PIN(160, GPIOE, 31),
212 };
213
214 static struct vega_irq vega_irq_map[] =
215 {
216 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
217 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
218 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
219 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
220 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
221 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
222 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
223 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
224 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
225 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
226 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
227 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
228 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
229 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
230 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
231 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
232 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
233 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
234 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
235 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
236 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
237 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
238 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
239 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
240 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
241 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
242 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
243 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
244 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
245 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
246 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
247 {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }
248 };
249
gpio_isr(GPIO_Type * base,rt_uint32_t gpio_pin)250 void gpio_isr(GPIO_Type* base, rt_uint32_t gpio_pin)
251 {
252 if((GPIO_GetPinsInterruptFlags(base) & (1 << gpio_pin)) != 0)
253 {
254 GPIO_ClearPinsInterruptFlags(base, gpio_pin);
255
256 if(vega_irq_map[gpio_pin].irq_info.hdr != RT_NULL)
257 {
258 vega_irq_map[gpio_pin].irq_info.hdr(vega_irq_map[gpio_pin].irq_info.args);
259 }
260 }
261 }
262
vega_get_irqnum(GPIO_Type * gpio,rt_uint32_t gpio_pin)263 static IRQn_Type vega_get_irqnum(GPIO_Type *gpio, rt_uint32_t gpio_pin)
264 {
265 IRQn_Type irq_num = NotAvail_IRQn; /* Invalid interrupt number */
266
267 if(gpio == GPIOA)
268 {
269 irq_num = PORTA_IRQn;
270 }
271 else if(gpio == GPIOB)
272 {
273 irq_num = PORTB_IRQn;
274 }
275 else if(gpio == GPIOC)
276 {
277 irq_num = PORTC_IRQn;
278 }
279 else if(gpio == GPIOD)
280 {
281 irq_num = PORTD_IRQn;
282 }
283 else if(gpio == GPIOE)
284 {
285 irq_num = PORTE_IRQn;
286 }
287
288 return irq_num;
289 }
290
vega_pin_mode(rt_device_t dev,rt_base_t pin,rt_uint8_t mode)291 static void vega_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
292 {
293 clock_ip_name_t clock;
294 gpio_pin_config_t gpio;
295 rt_uint32_t config_value = 0;
296
297 if((pin > __ARRAY_LEN(vega_pin_map)) || (pin == 0))
298 {
299 return;
300 }
301
302 if (vega_pin_map[pin].gpio == GPIOA)
303 clock = kCLOCK_PortA;
304 if (vega_pin_map[pin].gpio == GPIOB)
305 clock = kCLOCK_PortB;
306 if (vega_pin_map[pin].gpio == GPIOC)
307 clock = kCLOCK_PortC;
308 if (vega_pin_map[pin].gpio == GPIOD)
309 clock = kCLOCK_PortD;
310 if (vega_pin_map[pin].gpio == GPIOE)
311 clock = kCLOCK_PortE;
312
313 CLOCK_EnableClock(clock);
314
315 gpio.outputLogic = 0;
316
317 switch(mode)
318 {
319 case PIN_MODE_OUTPUT:
320 {
321 config_value = 0x1030U;
322 gpio.pinDirection = kGPIO_DigitalOutput;
323 }
324 break;
325
326 case PIN_MODE_INPUT:
327 {
328 config_value = 0x1030U;
329 gpio.pinDirection = kGPIO_DigitalInput;
330 }
331 break;
332
333 case PIN_MODE_INPUT_PULLDOWN:
334 {
335 config_value = 0x1030U;
336 gpio.pinDirection = kGPIO_DigitalInput;
337 }
338 break;
339
340 case PIN_MODE_INPUT_PULLUP:
341 {
342 config_value = 0x5030U;
343 gpio.pinDirection = kGPIO_DigitalInput;
344 }
345 break;
346
347 case PIN_MODE_OUTPUT_OD:
348 {
349 config_value = 0x1830U;
350 gpio.pinDirection = kGPIO_DigitalOutput;
351 }
352 break;
353 }
354
355 GPIO_PinInit(vega_pin_map[pin].gpio, vega_pin_map[pin].gpio_pin, &gpio);
356 }
357
vega_pin_read(rt_device_t dev,rt_base_t pin)358 static rt_ssize_t vega_pin_read(rt_device_t dev, rt_base_t pin)
359 {
360 uint32_t value;
361
362 value = GPIO_ReadPinInput(vega_pin_map[pin].gpio, vega_pin_map[pin].gpio_pin);
363 if (value) return PIN_HIGH;
364
365 return PIN_LOW;
366 }
367
vega_pin_write(rt_device_t dev,rt_base_t pin,rt_uint8_t value)368 static void vega_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
369 {
370 if (value == PIN_HIGH)
371 GPIO_SetPinsOutput(vega_pin_map[pin].gpio, 1U << vega_pin_map[pin].gpio_pin);
372 else
373 GPIO_ClearPinsOutput(vega_pin_map[pin].gpio, 1U << vega_pin_map[pin].gpio_pin);
374 }
375
vega_pin_attach_irq(struct rt_device * device,rt_base_t pin,rt_uint8_t mode,void (* hdr)(void * args),void * args)376 static rt_err_t vega_pin_attach_irq(struct rt_device *device, rt_base_t pin,
377 rt_uint8_t mode, void (*hdr)(void *args), void *args)
378 {
379 const struct vega_pin* pin_map = RT_NULL;
380 struct vega_irq* irq_map = RT_NULL;
381
382 pin_map = &vega_pin_map[pin];
383 irq_map = &vega_irq_map[vega_pin_map[pin].gpio_pin];
384
385 if(pin_map == RT_NULL || irq_map == RT_NULL)
386 {
387 return -RT_ENOSYS;
388 }
389
390 if(irq_map->enable == PIN_IRQ_ENABLE)
391 {
392 return -RT_EBUSY;
393 }
394
395 irq_map->irq_info.pin = pin;
396 irq_map->irq_info.hdr = hdr;
397 irq_map->irq_info.mode = mode;
398 irq_map->irq_info.args = args;
399
400 return RT_EOK;
401 }
402
vega_pin_detach_irq(struct rt_device * device,rt_base_t pin)403 static rt_err_t vega_pin_detach_irq(struct rt_device *device, rt_base_t pin)
404 {
405 const struct vega_pin* pin_map = RT_NULL;
406 struct vega_irq* irq_map = RT_NULL;
407
408 pin_map = &vega_pin_map[pin];
409 irq_map = &vega_irq_map[vega_pin_map[pin].gpio_pin];
410
411 if(pin_map == RT_NULL || irq_map == RT_NULL)
412 {
413 return -RT_ENOSYS;
414 }
415
416 if(irq_map->enable == PIN_IRQ_DISABLE)
417 {
418 return RT_EOK;
419 }
420
421 irq_map->irq_info.pin = PIN_IRQ_PIN_NONE;
422 irq_map->irq_info.hdr = RT_NULL;
423 irq_map->irq_info.mode = PIN_IRQ_MODE_RISING;
424 irq_map->irq_info.args = RT_NULL;
425
426 return RT_EOK;
427 }
428
vega_pin_irq_enable(struct rt_device * device,rt_base_t pin,rt_uint8_t enabled)429 static rt_err_t vega_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
430 {
431 gpio_pin_config_t gpio;
432 IRQn_Type irq_num;
433 rt_uint32_t config_value = 0x1b0a0;
434
435 const struct vega_pin* pin_map = RT_NULL;
436 struct vega_irq* irq_map = RT_NULL;
437
438 pin_map = &vega_pin_map[pin];
439 irq_map = &vega_irq_map[vega_pin_map[pin].gpio_pin];
440
441 if(pin_map == RT_NULL || irq_map == RT_NULL)
442 {
443 return -RT_ENOSYS;
444 }
445
446 if(enabled == PIN_IRQ_ENABLE)
447 {
448 if(irq_map->enable == PIN_IRQ_ENABLE)
449 {
450 return -RT_EBUSY;
451 }
452
453 if(irq_map->irq_info.pin != pin)
454 {
455 return -RT_EIO;
456 }
457
458 irq_map->enable = PIN_IRQ_ENABLE;
459
460 gpio.pinDirection = kGPIO_DigitalInput;
461 gpio.outputLogic = 0;
462
463 irq_num = vega_get_irqnum(vega_pin_map[pin].gpio, vega_pin_map[pin].gpio_pin);
464
465 /* TODOL enable port */
466 EnableIRQ(irq_num);
467
468 GPIO_PinInit(vega_pin_map[pin].gpio, vega_pin_map[pin].gpio_pin, &gpio);
469 // GPIO_EnablePinsInterruptFlags(vega_pin_map[pin].gpio, 1U << vega_pin_map[pin].gpio_pin);
470 }
471 else if(enabled == PIN_IRQ_DISABLE)
472 {
473 if(irq_map->enable == PIN_IRQ_DISABLE)
474 {
475 return RT_EOK;
476 }
477
478 irq_map->enable = PIN_IRQ_DISABLE;
479 irq_num = vega_get_irqnum(vega_pin_map[pin].gpio, vega_pin_map[pin].gpio_pin);
480
481 DisableIRQ(irq_num);
482 }
483 else
484 {
485 return -RT_EINVAL;
486 }
487
488 return RT_EOK;
489 }
490
491 static const struct rt_pin_ops vega_pin_ops =
492 {
493 vega_pin_mode,
494 vega_pin_write,
495 vega_pin_read,
496
497 vega_pin_attach_irq,
498 vega_pin_detach_irq,
499 vega_pin_irq_enable,
500 RT_NULL,
501 };
502
rt_hw_pin_init(void)503 int rt_hw_pin_init(void)
504 {
505 int ret = RT_EOK;
506
507 ret = rt_device_pin_register("pin", &vega_pin_ops, RT_NULL);
508 return ret;
509 }
510 INIT_BOARD_EXPORT(rt_hw_pin_init);
511
512 #endif /*RT_USING_PIN */
513