1 /*""FILE COMMENT""******************************************************* 2 * System Name : ADC converter API for RX62Nxx 3 * File Name : r_pdl_adc_10.h 4 * Version : 1.02 5 * Contents : ADC function prototypes 6 * Customer : 7 * Model : 8 * Order : 9 * CPU : RX 10 * Compiler : RXC 11 * OS : 12 * Programmer : 13 * Note : 14 ************************************************************************ 15 * Copyright, 2011. Renesas Electronics Corporation 16 * and Renesas Solutions Corporation 17 ************************************************************************ 18 * History : 2011.04.08 19 * : Ver 1.02 20 * : CS-5 release. 21 *""FILE COMMENT END""**************************************************/ 22 23 #ifndef R_PDL_ADC_10_H 24 #define R_PDL_ADC_10_H 25 26 #include "r_pdl_common_defs_RX62Nxx.h" 27 28 /* Function prototypes */ 29 bool R_ADC_10_Create( 30 uint8_t, 31 uint32_t, 32 uint32_t, 33 float, 34 void *, 35 uint8_t 36 ); 37 bool R_ADC_10_Destroy( 38 uint8_t 39 ); 40 bool R_ADC_10_Control( 41 uint16_t 42 ); 43 bool R_ADC_10_Read( 44 uint8_t, 45 uint16_t * 46 ); 47 48 /* Scan mode */ 49 #define PDL_ADC_10_MODE_SINGLE 0x00000001u 50 #define PDL_ADC_10_MODE_CONTINUOUS_SCAN 0x00000002u 51 #define PDL_ADC_10_MODE_ONE_CYCLE_SCAN 0x00000004u 52 53 /* Channel selection */ 54 #define PDL_ADC_10_CHANNELS_OPTION_1 0x00000008u 55 #define PDL_ADC_10_CHANNELS_OPTION_2 0x00000010u 56 #define PDL_ADC_10_CHANNELS_OPTION_3 0x00000020u 57 #define PDL_ADC_10_CHANNELS_OPTION_4 0x00000040u 58 59 /* Trigger selection */ 60 #define PDL_ADC_10_TRIGGER_SOFTWARE 0x00000080u 61 #define PDL_ADC_10_TRIGGER_MTU0_MTU4_CMIC_A 0x00000100u 62 #define PDL_ADC_10_TRIGGER_TMR0_CM_A 0x00000200u 63 #define PDL_ADC_10_TRIGGER_ADTRG0 0x00000400u 64 #define PDL_ADC_10_TRIGGER_ADTRG1 0x00000800u 65 #define PDL_ADC_10_TRIGGER_MTU0_CMIC 0x00001000u 66 #define PDL_ADC_10_TRIGGER_MTU6_MTU10_CMIC_A 0x00002000u 67 #define PDL_ADC_10_TRIGGER_MTU4_CM 0x00004000u 68 #define PDL_ADC_10_TRIGGER_MTU10_CM 0x00008000u 69 70 /* Data alignment */ 71 #define PDL_ADC_10_DATA_ALIGNMENT_LEFT 0x00010000u 72 #define PDL_ADC_10_DATA_ALIGNMENT_RIGHT 0x00020000u 73 74 /* DMAC / DTC trigger control */ 75 #define PDL_ADC_10_DMAC_DTC_TRIGGER_DISABLE 0x00040000u 76 #define PDL_ADC_10_DMAC_TRIGGER_ENABLE 0x00080000u 77 #define PDL_ADC_10_DTC_TRIGGER_ENABLE 0x00100000u 78 79 /* Sampling time calcuation control */ 80 #define PDL_ADC_10_ADSSTR_CALCULATE 0x00200000u 81 #define PDL_ADC_10_ADSSTR_SPECIFY 0x00400000u 82 83 /* Pin selection */ 84 #define PDL_ADC_10_PIN_ADTRG0_A 0x00800000u 85 #define PDL_ADC_10_PIN_ADTRG0_B 0x01000000u 86 87 /* Self-Diagnostic */ 88 #define PDL_ADC_10_SINGLE_AN0_SW (PDL_ADC_10_MODE_SINGLE | \ 89 PDL_ADC_10_CHANNELS_OPTION_1 | \ 90 PDL_ADC_10_TRIGGER_SOFTWARE) 91 #define PDL_ADC_10_ADDIAGR_DISABLE 0x02000000u 92 #define PDL_ADC_10_ADDIAGR_VREF_0 0x04000000u 93 #define PDL_ADC_10_ADDIAGR_VREF_0_5 0x08000000u 94 #define PDL_ADC_10_ADDIAGR_VREF_1 0x10000000u 95 #define PDL_ADC_10_SELF_DIAGNOSTIC_DISABLE (PDL_ADC_10_ADDIAGR_DISABLE) 96 #define PDL_ADC_10_SELF_DIAGNOSTIC_VREF_0 (PDL_ADC_10_SINGLE_AN0_SW | PDL_ADC_10_ADDIAGR_VREF_0) 97 #define PDL_ADC_10_SELF_DIAGNOSTIC_VREF_0_5 (PDL_ADC_10_SINGLE_AN0_SW | PDL_ADC_10_ADDIAGR_VREF_0_5) 98 #define PDL_ADC_10_SELF_DIAGNOSTIC_VREF_1 (PDL_ADC_10_SINGLE_AN0_SW | PDL_ADC_10_ADDIAGR_VREF_1) 99 100 /* On / off control */ 101 #define PDL_ADC_10_0_ON 0x0001u 102 #define PDL_ADC_10_0_OFF 0x0002u 103 #define PDL_ADC_10_1_ON 0x0004u 104 #define PDL_ADC_10_1_OFF 0x0008u 105 106 /* CPU control */ 107 #define PDL_ADC_10_CPU_ON 0x0100u 108 #define PDL_ADC_10_CPU_OFF 0x0200u 109 110 #endif 111 /* End of file */ 112