1 /*""FILE COMMENT""******************************************************* 2 * System Name : DMAC API for RX62Nxx 3 * File Name : r_pdl_dmac.h 4 * Version : 1.02 5 * Contents : DMAC API header 6 * Customer : 7 * Model : 8 * Order : 9 * CPU : RX 10 * Compiler : RXC 11 * OS : Nothing 12 * Programmer : 13 * Note : 14 ************************************************************************ 15 * Copyright, 2011. Renesas Electronics Corporation 16 * and Renesas Solutions Corporation 17 ************************************************************************ 18 * History : 2011.04.08 19 * : Ver 1.02 20 * : CS-5 release. 21 *""FILE COMMENT END""**************************************************/ 22 23 #ifndef R_PDL_DMAC_H 24 #define R_PDL_DMAC_H 25 26 #include "r_pdl_common_defs_RX62Nxx.h" 27 28 /* Function prototypes */ 29 bool R_DMAC_Create( 30 uint8_t, 31 uint32_t, 32 uint8_t, 33 void *, 34 void *, 35 uint16_t, 36 uint16_t, 37 int32_t, 38 uint32_t, 39 uint32_t, 40 void *, 41 uint8_t 42 ); 43 bool R_DMAC_Destroy( 44 uint8_t 45 ); 46 bool R_DMAC_Control( 47 uint8_t, 48 uint16_t, 49 void *, 50 void *, 51 uint16_t, 52 uint16_t, 53 int32_t, 54 uint32_t, 55 uint32_t 56 ); 57 bool R_DMAC_GetStatus( 58 uint8_t, 59 uint8_t *, 60 uint32_t *, 61 uint32_t *, 62 uint16_t *, 63 uint16_t * 64 ); 65 66 /* Transfer mode selection */ 67 #define PDL_DMAC_NORMAL 0x00000001ul 68 #define PDL_DMAC_REPEAT 0x00000002ul 69 #define PDL_DMAC_BLOCK 0x00000004ul 70 #define PDL_DMAC_SOURCE 0x00000008ul 71 #define PDL_DMAC_DESTINATION 0x00000010ul 72 73 /* Address addition direction selection */ 74 #define PDL_DMAC_SOURCE_ADDRESS_FIXED 0x00000020ul 75 #define PDL_DMAC_SOURCE_ADDRESS_PLUS 0x00000040ul 76 #define PDL_DMAC_SOURCE_ADDRESS_MINUS 0x00000080ul 77 #define PDL_DMAC_SOURCE_ADDRESS_OFFSET 0x00000100ul 78 #define PDL_DMAC_DESTINATION_ADDRESS_FIXED 0x00000200ul 79 #define PDL_DMAC_DESTINATION_ADDRESS_PLUS 0x00000400ul 80 #define PDL_DMAC_DESTINATION_ADDRESS_MINUS 0x00000800ul 81 #define PDL_DMAC_DESTINATION_ADDRESS_OFFSET 0x00001000ul 82 83 /* Transfer data size */ 84 #define PDL_DMAC_SIZE_8 0x00002000ul 85 #define PDL_DMAC_SIZE_16 0x00004000ul 86 #define PDL_DMAC_SIZE_32 0x00008000ul 87 88 /* Interrupt generation */ 89 #define PDL_DMAC_IRQ_END 0x00010000ul 90 #define PDL_DMAC_IRQ_ESCAPE_END 0x00020000ul 91 #define PDL_DMAC_IRQ_REPEAT_SIZE_END 0x00040000ul 92 #define PDL_DMAC_IRQ_EXT_SOURCE 0x00080000ul 93 #define PDL_DMAC_IRQ_EXT_DESTINATION 0x00100000ul 94 95 /* Start trigger forwarding */ 96 #define PDL_DMAC_TRIGGER_CLEAR 0x00200000ul 97 #define PDL_DMAC_TRIGGER_FORWARD 0x00400000ul 98 99 /* DTC trigger control */ 100 #define PDL_DMAC_DTC_TRIGGER_DISABLE 0x00800000ul 101 #define PDL_DMAC_DTC_TRIGGER_ENABLE 0x01000000ul 102 103 /* DMAC activation source */ 104 #define PDL_DMAC_TRIGGER_SW 0x00u 105 #define PDL_DMAC_TRIGGER_CMT0 VECT_CMT0_CMI0 106 #define PDL_DMAC_TRIGGER_CMT1 VECT_CMT1_CMI1 107 #define PDL_DMAC_TRIGGER_CMT2 VECT_CMT2_CMI2 108 #define PDL_DMAC_TRIGGER_CMT3 VECT_CMT3_CMI3 109 #define PDL_DMAC_TRIGGER_USB0_D0 VECT_USB0_D0FIFO0 110 #define PDL_DMAC_TRIGGER_USB0_D1 VECT_USB0_D1FIFO0 111 #define PDL_DMAC_TRIGGER_USB1_D0 VECT_USB1_D0FIFO1 112 #define PDL_DMAC_TRIGGER_USB1_D1 VECT_USB1_D1FIFO1 113 #define PDL_DMAC_TRIGGER_SPI0_RX VECT_RSPI0_SPRI0 114 #define PDL_DMAC_TRIGGER_SPI0_TX VECT_RSPI0_SPTI0 115 #define PDL_DMAC_TRIGGER_SPI1_RX VECT_RSPI1_SPRI1 116 #define PDL_DMAC_TRIGGER_SPI1_TX VECT_RSPI1_SPTI1 117 #define PDL_DMAC_TRIGGER_IRQ0 VECT_ICU_IRQ0 118 #define PDL_DMAC_TRIGGER_IRQ1 VECT_ICU_IRQ1 119 #define PDL_DMAC_TRIGGER_IRQ2 VECT_ICU_IRQ2 120 #define PDL_DMAC_TRIGGER_IRQ3 VECT_ICU_IRQ3 121 #define PDL_DMAC_TRIGGER_ADC10_0 VECT_AD0_ADI0 122 #define PDL_DMAC_TRIGGER_ADC10_1 VECT_AD1_ADI1 123 #define PDL_DMAC_TRIGGER_ADC12 VECT_S12AD_ADI 124 #define PDL_DMAC_TRIGGER_MTU0 VECT_MTU0_TGIA0 125 #define PDL_DMAC_TRIGGER_MTU1 VECT_MTU1_TGIA1 126 #define PDL_DMAC_TRIGGER_MTU2 VECT_MTU2_TGIA2 127 #define PDL_DMAC_TRIGGER_MTU3 VECT_MTU3_TGIA3 128 #define PDL_DMAC_TRIGGER_MTU4 VECT_MTU4_TGIA4 129 #define PDL_DMAC_TRIGGER_MTU6 VECT_MTU6_TGIA6 130 #define PDL_DMAC_TRIGGER_MTU7 VECT_MTU7_TGIA7 131 #define PDL_DMAC_TRIGGER_MTU8 VECT_MTU8_TGIA8 132 #define PDL_DMAC_TRIGGER_MTU9 VECT_MTU9_TGIA9 133 #define PDL_DMAC_TRIGGER_MTU10 VECT_MTU10_TGIA10 134 #define PDL_DMAC_TRIGGER_SCI0_RX VECT_SCI0_RXI0 135 #define PDL_DMAC_TRIGGER_SCI0_TX VECT_SCI0_TXI0 136 #define PDL_DMAC_TRIGGER_SCI1_RX VECT_SCI1_RXI1 137 #define PDL_DMAC_TRIGGER_SCI1_TX VECT_SCI1_TXI1 138 #define PDL_DMAC_TRIGGER_SCI2_RX VECT_SCI2_RXI2 139 #define PDL_DMAC_TRIGGER_SCI2_TX VECT_SCI2_TXI2 140 #define PDL_DMAC_TRIGGER_SCI3_RX VECT_SCI3_RXI3 141 #define PDL_DMAC_TRIGGER_SCI3_TX VECT_SCI3_TXI3 142 #define PDL_DMAC_TRIGGER_SCI5_RX VECT_SCI5_RXI5 143 #define PDL_DMAC_TRIGGER_SCI5_TX VECT_SCI5_TXI5 144 #define PDL_DMAC_TRIGGER_SCI6_RX VECT_SCI6_RXI6 145 #define PDL_DMAC_TRIGGER_SCI6_TX VECT_SCI6_TXI6 146 #define PDL_DMAC_TRIGGER_IIC0_RX VECT_RIIC0_ICRXI0 147 #define PDL_DMAC_TRIGGER_IIC0_TX VECT_RIIC0_ICTXI0 148 #define PDL_DMAC_TRIGGER_IIC1_RX VECT_RIIC1_ICRXI1 149 #define PDL_DMAC_TRIGGER_IIC1_TX VECT_RIIC1_ICTXI1 150 151 /* Enable / suspend control */ 152 #define PDL_DMAC_ENABLE 0x0001u 153 #define PDL_DMAC_SUSPEND 0x0002u 154 155 /* Software trigger control */ 156 #define PDL_DMAC_START 0x0004u 157 #define PDL_DMAC_START_RUN 0x0008u 158 #define PDL_DMAC_STOP 0x0010u 159 160 /* Transfer end interrupt flag control */ 161 #define PDL_DMAC_CLEAR_DTIF 0x0020u 162 #define PDL_DMAC_CLEAR_ESIF 0x0040u 163 164 /* Modify registers selection */ 165 #define PDL_DMAC_UPDATE_SOURCE 0x0080u 166 #define PDL_DMAC_UPDATE_DESTINATION 0x0100u 167 #define PDL_DMAC_UPDATE_COUNT 0x0200u 168 #define PDL_DMAC_UPDATE_SIZE 0x0400u 169 #define PDL_DMAC_UPDATE_OFFSET 0x0800u 170 #define PDL_DMAC_UPDATE_REPEAT_SOURCE 0x1000u 171 #define PDL_DMAC_UPDATE_REPEAT_DESTINATION 0x2000u 172 173 #endif 174 /* End of file */ 175