1 #include <rtthread.h>
2 #include <dfs_fs.h>
3
4 #include "sd.h"
5
6 #include <AT91SAM7X.h>
7
8 // *****************************************************************************
9 // PIO DEFINITIONS FOR AT91SAM7X256
10 // *****************************************************************************
11 #define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
12 #define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data
13 #define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
14 #define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data
15 #define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
16 #define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data
17 #define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
18 #define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock
19 #define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
20 #define AT91C_PA12_SPI0_NPCS0 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
21 #define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
22 #define AT91C_PA13_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
23 #define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1
24 #define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
25 #define AT91C_PA14_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
26 #define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1
27 #define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
28 #define AT91C_PA15_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
29 #define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input
30 #define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
31 #define AT91C_PA16_SPI0_MISO ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave
32 #define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
33 #define AT91C_PA17_SPI0_MOSI ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave
34 #define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
35 #define AT91C_PA18_SPI0_SPCK ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock
36 #define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
37 #define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive
38 #define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
39 #define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
40 #define AT91C_PA2_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
41 #define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
42 #define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit
43 #define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
44 #define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync
45 #define AT91C_PA21_SPI1_NPCS0 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
46 #define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
47 #define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock
48 #define AT91C_PA22_SPI1_SPCK ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock
49 #define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
50 #define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data
51 #define AT91C_PA23_SPI1_MOSI ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave
52 #define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
53 #define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data
54 #define AT91C_PA24_SPI1_MISO ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave
55 #define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
56 #define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock
57 #define AT91C_PA25_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
58 #define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
59 #define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync
60 #define AT91C_PA26_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
61 #define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
62 #define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data
63 #define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3
64 #define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
65 #define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data
66 #define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
67 #define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input
68 #define AT91C_PA29_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
69 #define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
70 #define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send
71 #define AT91C_PA3_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
72 #define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
73 #define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0
74 #define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2
75 #define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
76 #define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send
77 #define AT91C_PA4_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
78 #define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
79 #define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data
80 #define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
81 #define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data
82 #define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
83 #define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock
84 #define AT91C_PA7_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
85 #define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
86 #define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send
87 #define AT91C_PA8_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
88 #define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
89 #define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send
90 #define AT91C_PA9_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
91 #define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0
92 #define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
93 #define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0
94 #define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1
95 #define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
96 #define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10
97 #define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
98 #define AT91C_PB10_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
99 #define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11
100 #define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
101 #define AT91C_PB11_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
102 #define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12
103 #define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
104 #define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input
105 #define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13
106 #define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
107 #define AT91C_PB13_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
108 #define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14
109 #define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
110 #define AT91C_PB14_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
111 #define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15
112 #define AT91C_PB15_ERXDV_ECRSDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
113 #define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16
114 #define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected
115 #define AT91C_PB16_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
116 #define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17
117 #define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock
118 #define AT91C_PB17_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
119 #define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18
120 #define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
121 #define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger
122 #define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19
123 #define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0
124 #define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input
125 #define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2
126 #define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
127 #define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20
128 #define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1
129 #define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0
130 #define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21
131 #define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2
132 #define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1
133 #define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22
134 #define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3
135 #define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2
136 #define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23
137 #define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
138 #define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect
139 #define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24
140 #define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
141 #define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready
142 #define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25
143 #define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
144 #define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready
145 #define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26
146 #define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
147 #define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator
148 #define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27
149 #define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
150 #define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0
151 #define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28
152 #define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
153 #define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1
154 #define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29
155 #define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1
156 #define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2
157 #define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3
158 #define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
159 #define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30
160 #define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2
161 #define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3
162 #define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4
163 #define AT91C_PB4_ECRS ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
164 #define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5
165 #define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
166 #define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6
167 #define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
168 #define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7
169 #define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error
170 #define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8
171 #define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
172 #define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9
173 #define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
174
175 #define CARD_WP_PIN AT91C_PIO_PA16
176 #define CARD_INS_PIN AT91C_PIO_PA15
177 #define CARD_PWR_PIN AT91C_PIO_PA12
178
179 typedef volatile unsigned int AT91S_REG;// Hardware register definition
180 // *****************************************************************************
181 // SOFTWARE API DEFINITION FOR Serial Parallel Interface
182 // *****************************************************************************
183 typedef struct _AT91S_SPI {
184 AT91S_REG SPI_CR; // Control Register
185 AT91S_REG SPI_MR; // Mode Register
186 AT91S_REG SPI_RDR; // Receive Data Register
187 AT91S_REG SPI_TDR; // Transmit Data Register
188 AT91S_REG SPI_SR; // Status Register
189 AT91S_REG SPI_IER; // Interrupt Enable Register
190 AT91S_REG SPI_IDR; // Interrupt Disable Register
191 AT91S_REG SPI_IMR; // Interrupt Mask Register
192 AT91S_REG Reserved0[4]; //
193 AT91S_REG SPI_CSR[4]; // Chip Select Register
194 AT91S_REG Reserved1[48]; //
195 AT91S_REG SPI_RPR; // Receive Pointer Register
196 AT91S_REG SPI_RCR; // Receive Counter Register
197 AT91S_REG SPI_TPR; // Transmit Pointer Register
198 AT91S_REG SPI_TCR; // Transmit Counter Register
199 AT91S_REG SPI_RNPR; // Receive Next Pointer Register
200 AT91S_REG SPI_RNCR; // Receive Next Counter Register
201 AT91S_REG SPI_TNPR; // Transmit Next Pointer Register
202 AT91S_REG SPI_TNCR; // Transmit Next Counter Register
203 AT91S_REG SPI_PTCR; // PDC Transfer Control Register
204 AT91S_REG SPI_PTSR; // PDC Transfer Status Register
205 } AT91S_SPI, *AT91PS_SPI;
206 static AT91PS_SPI pSPI = ((AT91PS_SPI) 0xFFFE0000);
207
208 // -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
209 #define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
210 #define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
211 #define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
212 #define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
213 // -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
214 #define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
215 #define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
216 #define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
217 #define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
218 #define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
219 #define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
220 #define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
221 #define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
222 #define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
223 #define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
224 // -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
225 #define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
226 #define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
227 // -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
228 #define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
229 #define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
230 // -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
231 #define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
232 #define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
233 #define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
234 #define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
235 #define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
236 #define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
237 #define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
238 #define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
239 #define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
240 #define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
241 #define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
242 // -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
243 // -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
244 // -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
245 // -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
246 #define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
247 #define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
248 #define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
249 #define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
250 #define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
251 #define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
252 #define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
253 #define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
254 #define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
255 #define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
256 #define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
257 #define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
258 #define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
259 #define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
260 #define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
261 #define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
262
263 #define CARD_SELECT_PIN AT91C_PA13_SPI0_NPCS1
264 #define SPI_CSR_NUM 0
265
266 #define SPI_SCBR_MIN 2
267
268 /* MMC/SD command (in SPI) */
269 #define CMD0 (0x40+0) /* GO_IDLE_STATE */
270 #define CMD1 (0x40+1) /* SEND_OP_COND */
271 #define CMD9 (0x40+9) /* SEND_CSD */
272 #define CMD10 (0x40+10) /* SEND_CID */
273 #define CMD12 (0x40+12) /* STOP_TRANSMISSION */
274 #define CMD17 (0x40+17) /* READ_SINGLE_BLOCK */
275 #define CMD18 (0x40+18) /* READ_MULTIPLE_BLOCK */
276 #define CMD24 (0x40+24) /* WRITE_BLOCK */
277 #define CMD25 (0x40+25) /* WRITE_MULTIPLE_BLOCK */
278 #define CMD58 (0x40+58) /* READ_OCR */
279
280 /* Control signals (Platform dependent) */
281 #define SELECT() (AT91C_PIOA_CODR = CARD_SELECT_PIN) /* MMC CS = L */
282 #define DESELECT() (AT91C_PIOA_SODR = CARD_SELECT_PIN) /* MMC CS = H */
283
284 #define SOCKWP CARD_WP_PIN /* Write protect switch (PB5) */
285 #define SOCKINS CARD_INS_PIN /* Card detect switch (PB4) */
286
287 #define POWER_ON() (AT91C_PIOA_CODR = CARD_PWR_PIN)
288 #define POWER_OFF() (AT91C_PIOA_SODR = CARD_PWR_PIN)
289
290 static struct rt_device sd;
291 static struct dfs_partition part;
292
AT91_spiSetSpeed(rt_uint8_t speed)293 static void AT91_spiSetSpeed(rt_uint8_t speed)
294 {
295 rt_uint32_t reg;
296
297 if ( speed < SPI_SCBR_MIN ) speed = SPI_SCBR_MIN;
298 if ( speed > 1 ) speed &= 0xFE;
299
300 reg = pSPI->SPI_CSR[SPI_CSR_NUM];
301 reg = ( reg & ~(AT91C_SPI_SCBR) ) | ( (rt_uint32_t)speed << 8 );
302 pSPI->SPI_CSR[SPI_CSR_NUM] = reg;
303 }
304
AT91_spi(rt_uint8_t outgoing)305 static rt_uint8_t AT91_spi(rt_uint8_t outgoing)
306 {
307 rt_uint8_t incoming;
308
309 while( !( pSPI->SPI_SR & AT91C_SPI_TDRE ) ); // transfer compl. wait
310 pSPI->SPI_TDR = (rt_uint16_t)( outgoing );
311
312 while( !( pSPI->SPI_SR & AT91C_SPI_RDRF ) ); // wait for char
313 incoming = (rt_uint8_t)( pSPI->SPI_RDR );
314
315 return incoming;
316 }
317
318 /*--------------------------------*/
319 /* Transmit a rt_uint8_t to MMC via SPI */
320 /* (Platform dependent) */
xmit_spi(rt_uint8_t dat)321 rt_inline void xmit_spi(rt_uint8_t dat)
322 {
323 AT91_spi(dat);
324 }
325
326 /*---------------------------------*/
327 /* Receive a rt_uint8_t from MMC via SPI */
328 /* (Platform dependent) */
rcvr_spi(void)329 rt_inline rt_uint8_t rcvr_spi(void)
330 {
331 return AT91_spi(0xff);
332 }
333
334 /* Alternative "macro" (not at AT91 so far) to receive data fast */
rcvr_spi_m(rt_uint8_t * dst)335 static void rcvr_spi_m(rt_uint8_t *dst)
336 {
337 *dst = rcvr_spi();
338 }
339
340 /*---------------------*/
341 /* Wait for card ready */
wait_ready()342 static rt_uint8_t wait_ready ()
343 {
344 rt_uint8_t res;
345
346 rcvr_spi();
347 do
348 {
349 res = rcvr_spi();
350 } while ((res != 0xFF));
351
352 return res;
353 }
354
355 /*--------------------------------*/
356 /* Receive a data packet from MMC */
357
rcvr_datablock(rt_uint8_t * buff,rt_uint8_t wc)358 rt_bool_t rcvr_datablock (rt_uint8_t *buff, rt_uint8_t wc)
359 {
360 rt_uint8_t token;
361
362 {
363 /* Wait for data packet in timeout of 100ms */
364 token = rcvr_spi();
365 }while ((token == 0xFF));
366
367 if(token != 0xFE) return RT_FALSE; /* If not valid data token, retutn with error */
368
369 do
370 {
371 /* Receive the data block into buffer */
372 rcvr_spi_m(buff++);
373 rcvr_spi_m(buff++);
374 } while (--wc);
375
376 rcvr_spi(); /* Discard CRC */
377 rcvr_spi();
378
379 return RT_TRUE; /* Return with success */
380 }
381
382 /*---------------------------*/
383 /* Send a data packet to MMC */
xmit_datablock(const rt_uint8_t * buff,rt_uint8_t token)384 static rt_bool_t xmit_datablock(const rt_uint8_t *buff, rt_uint8_t token)
385 {
386 rt_uint8_t resp, wc = 0;
387
388 if (wait_ready() != 0xFF) return RT_FALSE;
389
390 xmit_spi(token); /* Xmit data token */
391 if (token != 0xFD)
392 { /* Is data token */
393 do
394 {
395 /* Xmit the 512 rt_uint8_t data block to MMC */
396 xmit_spi(*buff++);
397 xmit_spi(*buff++);
398 } while (--wc);
399
400 xmit_spi(0xFF); /* CRC (Dummy) */
401 xmit_spi(0xFF);
402 resp = rcvr_spi(); /* Reveive data response */
403
404 if ((resp & 0x1F) != 0x05) /* If not accepted, return with error */
405 return RT_FALSE;
406 }
407
408 return RT_TRUE;
409 }
410
411 /*------------------------------*/
412 /* Send a command packet to MMC */
send_cmd(rt_uint8_t cmd,rt_uint32_t arg)413 rt_uint8_t send_cmd (rt_uint8_t cmd, rt_uint32_t arg)
414 {
415 rt_uint8_t n, res;
416
417 if (wait_ready() != 0xFF) return 0xFF;
418
419 /* Send command packet */
420 xmit_spi(cmd); /* Command */
421 xmit_spi((rt_uint8_t)(arg >> 24)); /* Argument[31..24] */
422 xmit_spi((rt_uint8_t)(arg >> 16)); /* Argument[23..16] */
423 xmit_spi((rt_uint8_t)(arg >> 8)); /* Argument[15..8] */
424 xmit_spi((rt_uint8_t)arg); /* Argument[7..0] */
425 xmit_spi(0x95); /* CRC (valid for only CMD0) */
426
427 /* Receive command response */
428 if (cmd == CMD12) rcvr_spi(); /* Skip a stuff rt_uint8_t when stop reading */
429 n = 10; /* Wait for a valid response in timeout of 10 attempts */
430 do
431 {
432 res = rcvr_spi();
433 }
434 while ((res & 0x80) && --n);
435
436 return res; /* Return with the response value */
437 }
438
rt_sdcard_init(rt_device_t dev)439 static rt_err_t rt_sdcard_init(rt_device_t dev)
440 {
441 return RT_EOK;
442 }
443
rt_sdcard_open(rt_device_t dev,rt_uint16_t oflag)444 static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag)
445 {
446 return RT_EOK;
447 }
448
rt_sdcard_close(rt_device_t dev)449 static rt_err_t rt_sdcard_close(rt_device_t dev)
450 {
451 return RT_EOK;
452 }
453
rt_sdcard_read(rt_device_t dev,rt_off_t pos,void * buffer,rt_size_t size)454 static rt_ssize_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
455 {
456 rt_uint8_t count;
457
458 count = size / 512;
459
460 /* CS = L */
461 SELECT();
462
463 /* append partition offset */
464 pos += part.offset * 512;
465
466 if (count == 1)
467 { /* Single block read */
468 if ((send_cmd(CMD17, pos) == 0) /* READ_SINGLE_BLOCK */
469 && rcvr_datablock(buffer, (rt_uint8_t)(512/2)))
470 count = 0;
471 else
472 count = 1;
473 }
474 else
475 { /* Multiple block read */
476 if (send_cmd(CMD18, pos) == 0)
477 {
478 rt_uint8_t* ptr;
479
480 ptr = buffer;
481 do
482 {
483 if (!rcvr_datablock(ptr, (rt_uint8_t)(512/2))) break;
484 ptr += 512;
485 } while (--count);
486
487 send_cmd(CMD12, 0); /* STOP_TRANSMISSION */
488 }
489 }
490
491 DESELECT(); /* CS = H */
492 rcvr_spi(); /* Idle (Release DO) */
493
494 if (count)
495 {
496 // rt_set_errno(-RT_ERROR);
497 return 0;
498 }
499
500 return size / 512;
501 }
502
rt_sdcard_write(rt_device_t dev,rt_off_t pos,const void * buffer,rt_size_t size)503 static rt_ssize_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
504 {
505 rt_uint8_t count;
506
507 count = size / 512;
508
509 /* CS = L */
510 SELECT();
511
512 /* append partition offset */
513 pos += part.offset * 512;
514
515 if (count == 1)
516 {
517 /* Single block write */
518 if ((send_cmd(CMD24, pos) == 0) /* WRITE_BLOCK */
519 && xmit_datablock(buffer, 0xFE))
520 count = 0;
521 else
522 count = 1;
523 }
524 else
525 {
526 /* Multiple block write */
527 if (send_cmd(CMD25, pos) == 0)
528 {
529 rt_uint8_t *ptr;
530
531 ptr = (rt_uint8_t *)buffer;
532 do
533 {
534 if (!xmit_datablock(ptr, 0xFC)) break;
535 ptr += 512;
536 } while (--count);
537
538 if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */
539 count = 1;
540 }
541 }
542
543 DESELECT(); /* CS = H */
544 rcvr_spi(); /* Idle (Release DO) */
545
546 if (count)
547 {
548 rt_set_errno(-RT_ERROR);
549 return 0;
550 }
551
552 return size;
553 }
554
rt_sdcard_control(rt_device_t dev,int cmd,void * args)555 static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
556 {
557 return RT_EOK;
558 }
559
rt_hw_sdcard_init()560 void rt_hw_sdcard_init()
561 {
562 rt_uint32_t n;
563 rt_uint8_t* sector;
564
565 sd.type = RT_Device_Class_Block;
566 sd.init = rt_sdcard_init;
567 sd.open = rt_sdcard_open;
568 sd.close = rt_sdcard_close;
569 sd.read = rt_sdcard_read;
570 sd.write = rt_sdcard_write;
571 sd.control = rt_sdcard_control;
572 sd.user_data = RT_NULL;
573
574 AT91C_PIOA_PER = CARD_PWR_PIN; // enable GPIO of CS-pin
575 AT91C_PIOA_CODR = CARD_PWR_PIN; // set high
576 AT91C_PIOA_OER = CARD_PWR_PIN; // output enable
577
578 for (n = 0; n < 3000; n ++) ;
579
580 // disable PIO from controlling MOSI, MISO, SCK (=hand over to SPI)
581 // keep CS untouched - used as GPIO pin during init
582 AT91C_PIOA_PDR = AT91C_PA16_SPI0_MISO | AT91C_PA17_SPI0_MOSI | AT91C_PA18_SPI0_SPCK; // | NCPS_PDR_BIT;
583 // set pin-functions in PIO Controller
584 AT91C_PIOA_ASR = AT91C_PA16_SPI0_MISO | AT91C_PA17_SPI0_MOSI | AT91C_PA18_SPI0_SPCK; /// not here: | NCPS_ASR_BIT;
585
586 // set chip-select as output high (unselect card)
587 AT91C_PIOA_PER = CARD_SELECT_PIN; // enable GPIO of CS-pin
588 AT91C_PIOA_SODR = CARD_SELECT_PIN; // set high
589 AT91C_PIOA_OER = CARD_SELECT_PIN; // output enable
590
591 // enable peripheral clock for SPI ( PID Bit 5 )
592 AT91C_PMC_PCER = ( (rt_uint32_t) 1 << AT91C_ID_SPI0 ); // n.b. IDs are just bit-numbers
593
594 // SPI enable and reset
595 pSPI->SPI_CR = AT91C_SPI_SPIEN | AT91C_SPI_SWRST;
596
597 // SPI mode: master, FDIV=0, fault detection disabled
598 pSPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS;
599
600 // set chip-select-register
601 // 8 bits per transfer, CPOL=1, ClockPhase=0, DLYBCT = 0
602 pSPI->SPI_CSR[SPI_CSR_NUM] = AT91C_SPI_CPOL | AT91C_SPI_BITS_8;
603
604 // slow during init
605 AT91_spiSetSpeed(0xFE);
606
607 // enable
608 pSPI->SPI_CR = AT91C_SPI_SPIEN;
609
610 n = 10; /* Dummy clock */
611 do
612 {
613 rcvr_spi();
614 } while (--n);
615
616 SELECT(); /* CS = L */
617 if (send_cmd(CMD0, 0) == 1)
618 {
619 /* Enter Idle state */
620 while (send_cmd(CMD1, 0));
621 }
622
623 DESELECT(); /* CS = H */
624 rcvr_spi(); /* Idle (Release DO) */
625
626 AT91_spiSetSpeed(SPI_SCBR_MIN);
627
628 /* get the first sector to read partition table */
629 sector = (rt_uint8_t*) rt_malloc (512);
630 if (sector == RT_NULL)
631 {
632 rt_kprintf("allocate partition sector buffer failed\n");
633 return;
634 }
635
636 n = rt_sdcard_read((rt_device_t)&sd, 0, sector, 512);
637 if (n == 512)
638 {
639 rt_err_t status;
640
641 /* get the first partition */
642 status = dfs_filesystem_get_partition(&part, sector, 0);
643 if (status != RT_EOK)
644 {
645 /* there is no partition table */
646 part.offset = 0;
647 part.size = 0;
648 }
649 }
650 else
651 {
652 /* there is no partition table */
653 part.offset = 0;
654 part.size = 0;
655 }
656
657 /* release sector buffer */
658 rt_free(sector);
659
660 /* register sd device */
661 rt_device_register(&sd, "sd", RT_DEVICE_FLAG_RDWR);
662 }
663