1 /** 2 * \file 3 * 4 * \brief SAM SERCOM I2C Common Driver 5 * 6 * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 18 * 2. Redistributions in binary form must reproduce the above copyright notice, 19 * this list of conditions and the following disclaimer in the documentation 20 * and/or other materials provided with the distribution. 21 * 22 * 3. The name of Atmel may not be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * 4. This software may only be redistributed and used in connection with an 26 * Atmel microcontroller product. 27 * 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * \asf_license_stop 41 * 42 */ 43 /* 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 45 */ 46 #ifndef I2C_COMMON_H_INCLUDED 47 #define I2C_COMMON_H_INCLUDED 48 49 #include <compiler.h> 50 #include <sercom.h> 51 52 #ifdef __cplusplus 53 extern "C" { 54 #endif 55 56 /** 57 * \if (I2C_MASTER_MODE && I2C_SLAVE_MODE) 58 * \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C (SERCOM I2C) Driver 59 * \elseif I2C_MASTER_MODE 60 * \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C Master Mode (SERCOM I2C) Driver 61 * \elseif I2C_SLAVE_MODE 62 * \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C Slave Mode (SERCOM I2C) Driver 63 * \endif 64 * 65 * This driver for Atmel® | SMART ARM®-based microcontrollers provides 66 * an interface for the configuration and management of the device's SERCOM 67 * I<SUP>2</SUP>C module, for the transfer of data via an I<SUP>2</SUP>C bus. 68 * The following driver API modes are covered by this manual: 69 * 70 * \if I2C_MASTER_MODE 71 * - Master Mode Polled APIs 72 * \endif 73 * \if I2C_MASTER_CALLBACK_MODE 74 * - Master Mode Callback APIs 75 * \endif 76 * \if I2C_SLAVE_MODE 77 * - Slave Mode Polled APIs 78 * \endif 79 * \if I2C_SLAVE_CALLBACK_MODE 80 * - Slave Mode Callback APIs 81 * \endif 82 * 83 * The following peripheral is used by this module: 84 * - SERCOM (Serial Communication Interface) 85 * 86 * The following devices can use this module: 87 * - Atmel | SMART SAM D20/D21 88 * - Atmel | SMART SAM R21 89 * - Atmel | SMART SAM D09/D10/D11 90 * - Atmel | SMART SAM L21/L22 91 * - Atmel | SMART SAM DA1 92 * - Atmel | SMART SAM C20/C21 93 * - Atmel | SMART SAM HA1 94 * 95 * The outline of this documentation is as follows: 96 * - \ref asfdoc_sam0_sercom_i2c_prerequisites 97 * - \ref asfdoc_sam0_sercom_i2c_overview 98 * - \ref asfdoc_sam0_sercom_i2c_special_considerations 99 * - \ref asfdoc_sam0_sercom_i2c_extra 100 * - \ref asfdoc_sam0_sercom_i2c_examples 101 * - \ref asfdoc_sam0_sercom_i2c_api_overview 102 * 103 * \section asfdoc_sam0_sercom_i2c_prerequisites Prerequisites 104 * There are no prerequisites. 105 * 106 * \section asfdoc_sam0_sercom_i2c_overview Module Overview 107 * The outline of this section is as follows: 108 * - \ref asfdoc_sam0_sercom_i2c_module_features 109 * - \ref asfdoc_sam0_sercom_i2c_functional_desc 110 * - \ref asfdoc_sam0_sercom_i2c_bus_topology 111 * - \ref asfdoc_sam0_sercom_i2c_transactions 112 * - \ref asfdoc_sam0_sercom_i2c_multi_master 113 * - \ref asfdoc_sam0_sercom_i2c_bus_states 114 * - \ref asfdoc_sam0_sercom_i2c_timeout 115 * - \ref asfdoc_sam0_sercom_i2c_sleep_modes 116 * 117 * \subsection asfdoc_sam0_sercom_i2c_module_features Driver Feature Macro Definition 118 * <table> 119 * <tr> 120 * <th>Driver Feature Macro</th> 121 * <th>Supported devices</th> 122 * </tr> 123 * <tr> 124 * <td>FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED</td> 125 * <td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1</td> 126 * </tr> 127 * <tr> 128 * <td>FEATURE_I2C_10_BIT_ADDRESS</td> 129 * <td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1</td> 130 * </tr> 131 * <tr> 132 * <td>FEATURE_I2C_SCL_STRETCH_MODE</td> 133 * <td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1</td> 134 * </tr> 135 * <tr> 136 * <td>FEATURE_I2C_SCL_EXTEND_TIMEOUT</td> 137 * <td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1</td> 138 * </tr> 139 * </table> 140 * \note The specific features are only available in the driver when the selected 141 * device supports those features. 142 * \note When using the I2C high-speed mode for off-board communication, 143 * there are various high frequency interference, which can lead to distortion of the signals 144 * and communication failure. When using Xplained Pro boards in order to test I2C high-speed 145 * communication, the following recommendation should be followed: 146 * - Use the SDA-line on PA08 and SCL-line on PA09 for both boards. This will provide stronger 147 * pull-ups on both SDA and SCL. 148 * - The SCL should not be higher than 1.5MHz. 149 * 150 * \subsection asfdoc_sam0_sercom_i2c_functional_desc Functional Description 151 * The I<SUP>2</SUP>C provides a simple two-wire bidirectional bus consisting of a 152 * wired-AND type serial clock line (SCL) and a wired-AND type serial data line 153 * (SDA). 154 * 155 * The I<SUP>2</SUP>C bus provides a simple, but efficient method of interconnecting 156 * multiple master and slave devices. An arbitration mechanism is provided for 157 * resolving bus ownership between masters, as only one master device may own 158 * the bus at any given time. The arbitration mechanism relies on the wired-AND 159 * connections to avoid bus drivers short-circuiting. 160 * 161 * A unique address is assigned to all slave devices connected to the bus. A 162 * device can contain both master and slave logic, and can emulate multiple 163 * slave devices by responding to more than one address. 164 * 165 * \subsection asfdoc_sam0_sercom_i2c_bus_topology Bus Topology 166 * The I<SUP>2</SUP>C bus topology is illustrated in 167 * \ref asfdoc_sam0_sercom_i2c_bus_topology_figure "the figure below". The pull-up 168 * resistors (Rs) will provide a high level on the bus lines when none of the 169 * I<SUP>2</SUP>C devices are driving the bus. These are optional, and can be 170 * replaced with a constant current source. 171 * 172 * \anchor asfdoc_sam0_sercom_i2c_bus_topology_figure 173 * \image html bus_topology.svg "I2C Bus Topology" Width=100% 174 * 175 * \subsection asfdoc_sam0_sercom_i2c_transactions Transactions 176 * The I<SUP>2</SUP>C standard defines three fundamental transaction formats: 177 * - Master Write 178 * - The master transmits data packets to the slave after addressing it 179 * - Master Read 180 * - The slave transmits data packets to the master after being addressed 181 * - Combined Read/Write 182 * - A combined transaction consists of several write and read transactions 183 * 184 * A data transfer starts with the master issuing a \b Start condition on the 185 * bus, followed by the address of the slave together with a bit to indicate 186 * whether the master wants to read from or write to the slave. 187 * The addressed slave must respond to this by sending an \b ACK back to the 188 * master. 189 * 190 * After this, data packets are sent from the master or slave, according to the 191 * read/write bit. Each packet must be acknowledged (ACK) or not 192 * acknowledged (NACK) by the receiver. 193 * 194 * If a slave responds with a NACK, the master must assume that the slave 195 * cannot receive any more data and cancel the write operation. 196 * 197 * The master completes a transaction by issuing a \b Stop condition. 198 * 199 * A master can issue multiple \b Start conditions during a transaction; this 200 * is then called a \b Repeated \b Start condition. 201 * 202 * \subsubsection asfdoc_sam0_sercom_i2c_address_packets Address Packets 203 * The slave address consists of seven bits. The 8<SUP>th</SUP> bit in the transfer 204 * determines the data direction (read or write). An address packet always 205 * succeeds a \b Start or \b Repeated \b Start condition. The 8<SUP>th</SUP> bit is handled 206 * in the driver, and the user will only have to provide the 7-bit address. 207 * 208 * \subsubsection asfdoc_sam0_sercom_i2c_data_packets Data Packets 209 * Data packets are nine bits long, consisting of one 8-bit data byte, and an 210 * acknowledgement bit. Data packets follow either an address packet or another 211 * data packet on the bus. 212 * 213 * \subsubsection asfdoc_sam0_sercom_i2c_trans_examples Transaction Examples 214 * The gray bits in the following examples are sent from master to slave, and 215 * the white bits are sent from slave to master. 216 * Example of a read transaction is shown in 217 * \ref asfdoc_sam0_sercom_i2c_trans_examples_i2c_read "the figure below". Here, the 218 * master first issues a \b Start condition and gets ownership of the bus. An 219 * address packet with the direction flag set to read is then sent and 220 * acknowledged by the slave. Then the slave sends one data packet which is 221 * acknowledged by the master. The slave sends another packet, which is not 222 * acknowledged by the master and indicates that the master will terminate the 223 * transaction. In the end, the transaction is terminated by the master issuing 224 * a \b Stop condition. 225 * 226 * \anchor asfdoc_sam0_sercom_i2c_trans_examples_i2c_read 227 * \image html i2c_read.svg "I2C Packet Read" Width=100% 228 * 229 * Example of a write transaction is shown in 230 * \ref asfdoc_sam0_sercom_i2c_trans_examples_i2c_write "the figure below". Here, the 231 * master first issues a \b Start condition and gets ownership of the bus. An 232 * address packet with the dir flag set to write is then sent and acknowledged 233 * by the slave. Then the master sends two data packets, each acknowledged by 234 * the slave. In the end, the transaction is terminated by the master issuing 235 * a \b Stop condition. 236 * 237 * \anchor asfdoc_sam0_sercom_i2c_trans_examples_i2c_write 238 * \image html i2c_write.svg "I2C Packet Write" Width=100% 239 * 240 * \subsubsection asfdoc_sam0_sercom_i2c_packet_timeout Packet Timeout 241 * When a master sends an I<SUP>2</SUP>C packet, there is no way of 242 * being sure that a slave will acknowledge the packet. To avoid stalling the 243 * device forever while waiting for an acknowledge, a user selectable timeout 244 * is provided in the \ref i2c_master_config struct which 245 * lets the driver exit a read or write operation after the specified time. 246 * The function will then return the STATUS_ERR_TIMEOUT flag. 247 * 248 * This is also the case for the slave when using the functions postfixed 249 * \c _wait. 250 * 251 * The time before the timeout occurs, will be the same as 252 * for \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "unknown bus state" timeout. 253 * 254 * \subsubsection asfdoc_sam0_sercom_i2c_repeated_start Repeated Start 255 * To issue a \b Repeated \b Start, the functions postfixed \c _no_stop must be 256 * used. 257 * These functions will not send a \b Stop condition when the transfer is done, 258 * thus the next transfer will start with a \b Repeated \b Start. To end the 259 * transaction, the functions without the \c _no_stop postfix must be used 260 * for the last read/write. 261 * 262 * \subsection asfdoc_sam0_sercom_i2c_multi_master Multi Master 263 * In a multi master environment, arbitration of the bus is important, as only 264 * one master can own the bus at any point. 265 * 266 * \subsubsection asfdoc_sam0_sercom_i2c_arbitration Arbitration 267 * 268 * \par Clock stretching 269 * The serial clock line is always driven by a master device. However, all 270 * devices connected to the bus are allowed stretch the low period of the clock 271 * to slow down the overall clock frequency or to insert wait states while 272 * processing data. 273 * Both master and slave can randomly stretch the clock, which will force the 274 * other device into a wait-state until the clock line goes high again. 275 * 276 * \par Arbitration on the data line 277 * If two masters start transmitting at the same time, they will both transmit 278 * until one master detects that the other master is pulling the data line low. 279 * When this is detected, the master not pulling the line low, will stop the 280 * transmission and wait until the bus is idle. 281 * As it is the master trying to contact the slave with the lowest address that 282 * will get the bus ownership, this will create an arbitration scheme always 283 * prioritizing the slaves with the lowest address in case of a bus collision. 284 * 285 * \subsubsection asfdoc_sam0_sercom_i2c_clock_sync Clock Synchronization 286 * In situations where more than one master is trying to control the bus clock 287 * line at the same time, a clock synchronization algorithm based on the same 288 * principles used for clock stretching is necessary. 289 * 290 * 291 * \subsection asfdoc_sam0_sercom_i2c_bus_states Bus States 292 * As the I<SUP>2</SUP>C bus is limited to one transaction at the time, 293 * a master that wants to perform a bus transaction must wait until the bus is 294 * free. 295 * Because of this, it is necessary for all masters in a multi-master system to 296 * know the current status of the bus to be able to avoid conflicts and to 297 * ensure data integrity. 298 * \li \b IDLE No activity on the bus (between a \b Stop and a new \b Start 299 * condition) 300 * \li \b OWNER If the master initiates a transaction successfully 301 * \li \b BUSY If another master is driving the bus 302 * \li \b UNKNOWN If the master has recently been enabled or connected to 303 * the bus. Is forced to \b IDLE after given 304 * \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "timeout" when 305 * the master module is enabled 306 * 307 * The bus state diagram can be seen in 308 * \ref asfdoc_sam0_sercom_i2c_bus_states_figure "the figure below". 309 * \li S: Start condition 310 * \li P: Stop condition 311 * \li Sr: Repeated start condition 312 * \anchor asfdoc_sam0_sercom_i2c_bus_states_figure 313 * \image html bus_state_diagram.svg "I2C Bus State Diagram" Width=100% 314 * 315 * \subsection asfdoc_sam0_sercom_i2c_timeout Bus Timing 316 * Inactive bus timeout for the master and SDA hold time is configurable in the 317 * drivers. 318 * 319 * \subsubsection asfdoc_sam0_sercom_i2c_unknown_bus_timeout Unknown Bus State Timeout 320 * When a master is enabled or connected to the bus, the bus state will be 321 * unknown until either a given timeout or a stop command has occurred. The 322 * timeout is configurable in the \ref i2c_master_config struct. 323 * The timeout time will depend on toolchain and optimization level used, as 324 * the timeout is a loop incrementing a value until it reaches the specified 325 * timeout value. 326 * 327 * \subsubsection sda_hold SDA Hold Timeout 328 * When using the I<SUP>2</SUP>C in slave mode, it will be important to 329 * set a SDA hold time which assures that the master will be able to pick up 330 * the bit sent from the slave. The SDA hold time makes sure that this is the 331 * case by holding the data line low for a given period after the negative edge 332 * on the clock. 333 * 334 * The SDA hold time is also available for the master driver, but is not a 335 * necessity. 336 * 337 * \subsection asfdoc_sam0_sercom_i2c_sleep_modes Operation in Sleep Modes 338 * The I<SUP>2</SUP>C module can operate in all sleep modes by setting 339 * the run_in_standby Boolean in the \ref i2c_master_config or 340 * \ref i2c_slave_config struct. 341 * The operation in slave and master mode is shown in 342 * \ref asfdoc_sam0_sercom_i2c_sleep_modes_table "the table below". 343 * 344 * \anchor asfdoc_sam0_sercom_i2c_sleep_modes_table 345 * <table> 346 * <caption>I2C Standby Operations</caption> 347 * <tr> 348 * <th>Run in standby</th> 349 * <th>Slave</th> 350 * <th>Master</th> 351 * </tr> 352 * <tr> 353 * <td>false</td> 354 * <td>Disabled, all reception is dropped</td> 355 * <td>Generic Clock (GCLK) disabled when master is idle</td> 356 * </tr> 357 * <tr> 358 * <td>true</td> 359 * <td>Wake on address match when enabled</td> 360 * <td>GCLK enabled while in sleep modes</td> 361 * </tr> 362 * </table> 363 * 364 * 365 * \section asfdoc_sam0_sercom_i2c_special_considerations Special Considerations 366 * 367 * \if (I2C_MASTER_CALLBACK_MODE || I2C_SLAVE_CALLBACK_MODE) 368 * \subsection asfdoc_sam0_sercom_i2c_common_interrupt Interrupt-driven Operation 369 * While an interrupt-driven operation is in progress, subsequent calls to a 370 * write or read operation will return the STATUS_BUSY flag, indicating that 371 * only one operation is allowed at any given time. 372 * 373 * To check if another transmission can be initiated, the user can either call 374 * another transfer operation, or use the 375 * \ref i2c_master_get_job_status/\ref i2c_slave_get_job_status functions 376 * depending on mode. 377 * 378 * If the user would like to get callback from operations while using the 379 * interrupt-driven driver, the callback must be registered and then enabled 380 * using the "register_callback" and "enable_callback" functions. 381 * \else 382 * There are no special considerations for this driver for the APIs listed in 383 * this document. 384 * \endif 385 * 386 * \section asfdoc_sam0_sercom_i2c_extra Extra Information 387 * For extra information, see \ref asfdoc_sam0_sercom_i2c_extra_info_page. 388 * This includes: 389 * - \ref asfdoc_sam0_sercom_i2c_acronyms 390 * - \ref asfdoc_sam0_sercom_i2c_extra_dependencies 391 * - \ref asfdoc_sam0_sercom_i2c_extra_errata 392 * - \ref asfdoc_sam0_sercom_i2c_extra_history 393 * 394 * \section asfdoc_sam0_sercom_i2c_examples Examples 395 * 396 * For a list of examples related to this driver, see 397 * \ref asfdoc_sam0_sercom_i2c_exqsg. 398 * 399 * \section asfdoc_sam0_sercom_i2c_api_overview API Overview 400 * @{ 401 */ 402 403 /** 404 * \name Driver Feature Definition 405 * Define SERCOM I<SUP>2</SUP>C driver features set according to different device family. 406 * 407 * @{ 408 */ 409 #if (SAMD21) || (SAMR21) || (SAMD10) || (SAMD11) || (SAML21) || (SAMDA1) || \ 410 (SAMHA1) || (SAML22) || (SAMC20) || (SAMC21) || (SAMD09) || (SAMR30) || defined(__DOXYGEN__) 411 /** Fast mode plus and high speed support. */ 412 # define FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED 413 /** 10-bit address support */ 414 # define FEATURE_I2C_10_BIT_ADDRESS 415 /** SCL stretch mode support */ 416 # define FEATURE_I2C_SCL_STRETCH_MODE 417 /** SCL extend timeout support */ 418 # define FEATURE_I2C_SCL_EXTEND_TIMEOUT 419 # define FEATURE_I2C_DMA_SUPPORT 420 #endif 421 /*@}*/ 422 423 /** \brief Transfer direction 424 * 425 * For master: transfer direction or setting direction bit in address. 426 * For slave: direction of request from master. 427 */ 428 enum i2c_transfer_direction { 429 /** Master write operation is in progress */ 430 I2C_TRANSFER_WRITE = 0, 431 /** Master read operation is in progress */ 432 I2C_TRANSFER_READ = 1, 433 }; 434 435 /** @} */ 436 437 #ifdef __cplusplus 438 } 439 #endif 440 441 /** 442 * \page asfdoc_sam0_sercom_i2c_extra_info_page Extra Information for SERCOM I2C Driver 443 * 444 * \section asfdoc_sam0_sercom_i2c_acronyms Acronyms 445 * \ref asfdoc_sam0_sercom_i2c_acronyms_table "Below" is a table listing the acronyms 446 * used in this module, along with their intended meanings. 447 * 448 * \anchor asfdoc_sam0_sercom_i2c_acronyms_table 449 * <table> 450 * <caption>Acronyms</caption> 451 * <tr> 452 * <th>Acronym</th> 453 * <th>Description</th> 454 * </tr> 455 * <tr> 456 * <td>SDA</td> 457 * <td>Serial Data Line</td> 458 * </tr> 459 * <tr> 460 * <td>SCL</td> 461 * <td>Serial Clock Line</td> 462 * </tr> 463 * <tr> 464 * <td>SERCOM</td> 465 * <td>Serial Communication Interface</td> 466 * </tr> 467 * <tr> 468 * <td>DMA</td> 469 * <td>Direct Memory Access</td> 470 * </tr> 471 * </table> 472 * 473 * \section asfdoc_sam0_sercom_i2c_extra_dependencies Dependencies 474 * The I<SUP>2</SUP>C driver has the following dependencies: 475 * \li \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" 476 * 477 * 478 * \section asfdoc_sam0_sercom_i2c_extra_errata Errata 479 * There are no errata related to this driver. 480 * 481 * \section asfdoc_sam0_sercom_i2c_extra_history Module History 482 * \ref asfdoc_sam0_sercom_i2c_extra_history_table "Below" is an overview of the 483 * module history, detailing enhancements and fixes made to the module since 484 * its first release. The current version of this corresponds to the newest 485 * version listed in 486 * \ref asfdoc_sam0_sercom_i2c_extra_history_table "the table below". 487 * 488 * \anchor asfdoc_sam0_sercom_i2c_extra_history_table 489 * <table> 490 * <caption>Module History</caption> 491 * <tr> 492 * <th>Changelog</th> 493 * </tr> 494 * <tr> 495 * <td> 496 * \li Added 10-bit addressing and high speed support in SAM D21 497 * \li Separate structure i2c_packet into i2c_master_packet and i2c_slave packet 498 * </td> 499 * </tr> 500 * <tr> 501 * <td> 502 * \li Added support for SCL stretch and extended timeout hardware features in SAM D21 503 * \li Added fast mode plus support in SAM D21 504 * </td> 505 * </tr> 506 * <tr> 507 * <td>Fixed incorrect logical mask for determining if a bus error has 508 * occurred in I<SUP>2</SUP>C Slave mode 509 * </td> 510 * </tr> 511 * <tr> 512 * <td>Initial Release</td> 513 * </tr> 514 * </table> 515 */ 516 517 /** 518 * \page asfdoc_sam0_sercom_i2c_exqsg Examples for SERCOM I2C Driver 519 * 520 * This is a list of the available Quick Start guides (QSGs) and example 521 * applications for \ref asfdoc_sam0_sercom_i2c_group. QSGs are simple examples with 522 * step-by-step instructions to configure and use this driver in a selection of 523 * use cases. Note that a QSG can be compiled as a standalone application or be 524 * added to the user application. 525 * 526 * \if I2C_MASTER_MODE 527 * - \subpage asfdoc_sam0_sercom_i2c_master_basic_use_case "Quick Start Guide for the I2C Master module - Basic Use Case" 528 * \endif 529 * \if I2C_MASTER_CALLBACK_MODE 530 * - \subpage asfdoc_sam0_sercom_i2c_master_callback_use_case "Quick Start Guide for the I2C Master module - Callback Use Case" 531 * - \subpage asfdoc_sam0_sercom_i2c_master_dma_use_case "Quick Start Guide for the I2C Master module - DMA Use Case" 532 * \endif 533 * \if I2C_SLAVE_MODE 534 * - \subpage asfdoc_sam0_sercom_i2c_slave_basic_use_case "Quick Start Guide for the I2C Slave module - Basic Use Case" 535 * \endif 536 * \if I2C_SLAVE_CALLBACK_MODE 537 * - \subpage asfdoc_sam0_sercom_i2c_slave_callback_use_case "Quick Start Guide for the I2C Slave module - Callback Use Case" 538 * - \subpage asfdoc_sam0_sercom_i2c_slave_dma_use_case "Quick Start Guide for the I2C Slave module - DMA Use Case" 539 * \endif 540 * 541 * \page asfdoc_sam0_sercom_i2c_document_revision_history Document Revision History 542 * 543 * \if (I2C_MASTER_MODE || I2C_MASTER_CALLBACK_MODE) 544 * <table> 545 * <tr> 546 * <th>Doc. Rev.</th> 547 * <th>Date</th> 548 * <th>Comments</th> 549 * </tr> 550 * <tr> 551 * <td>42117E</td> 552 * <td>12/2015</td> 553 * <td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C21</td> 554 * </tr> 555 * <tr> 556 * <td>42117D</td> 557 * <td>12/2014</td> 558 * <td>Added support for 10-bit addressing and high speed in SAM D21. 559 * Added support for SAM R21 and SAM D10/D11.</td> 560 * </tr> 561 * <tr> 562 * <td>42117C</td> 563 * <td>01/2014</td> 564 * <td>Added support for SAM D21</td> 565 * </tr> 566 * <tr> 567 * <td>42117B</td> 568 * <td>06/2013</td> 569 * <td>Corrected documentation typos. Updated I<SUP>2</SUP>C Bus State Diagram.</td> 570 * </tr> 571 * <tr> 572 * <td>42117A</td> 573 * <td>06/2013</td> 574 * <td>Initial release</td> 575 * </tr> 576 * </table> 577 * \else 578 * <table> 579 * <tr> 580 * <th>Doc. Rev.</th> 581 * <th>Date</th> 582 * <th>Comments</th> 583 * </tr> 584 * <tr> 585 * <td>42116E</td> 586 * <td>12/2015</td> 587 * <td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C21</td> 588 * </tr> 589 * <tr> 590 * <td>42116D</td> 591 * <td>12/2014</td> 592 * <td>Added support for 10-bit addressing and high speed in SAM D21. 593 * Added support for SAM R21 and SAM D10/D11.</td> 594 * </tr> 595 * <tr> 596 * <td>42116C</td> 597 * <td>01/2014</td> 598 * <td>Added support for SAM D21</td> 599 * </tr> 600 * <tr> 601 * <td>42116B</td> 602 * <td>06/2013</td> 603 * <td>Corrected documentation typos. Updated I<SUP>2</SUP>C Bus State Diagram.</td> 604 * </tr> 605 * <tr> 606 * <td>42116A</td> 607 * <td>06/2013</td> 608 * <td>Initial release</td> 609 * </tr> 610 * </table> 611 *\endif 612 */ 613 614 #endif /* I2C_COMMON_H_INCLUDED */ 615