1 /** 2 * \file 3 * 4 * \brief Component description for NVMCTRL 5 * 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 18 * 2. Redistributions in binary form must reproduce the above copyright notice, 19 * this list of conditions and the following disclaimer in the documentation 20 * and/or other materials provided with the distribution. 21 * 22 * 3. The name of Atmel may not be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * 4. This software may only be redistributed and used in connection with an 26 * Atmel microcontroller product. 27 * 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * \asf_license_stop 41 * 42 */ 43 /* 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 45 */ 46 47 #ifndef _SAMD20_NVMCTRL_COMPONENT_ 48 #define _SAMD20_NVMCTRL_COMPONENT_ 49 50 /* ========================================================================== */ 51 /** SOFTWARE API DEFINITION FOR NVMCTRL */ 52 /* ========================================================================== */ 53 /** \addtogroup SAMD20_NVMCTRL Non-Volatile Memory Controller */ 54 /*@{*/ 55 56 #define NVMCTRL_U2207 57 #define REV_NVMCTRL 0x1061 58 59 /* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */ 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 61 typedef union { 62 struct { 63 uint16_t CMD:7; /*!< bit: 0.. 6 Command */ 64 uint16_t :1; /*!< bit: 7 Reserved */ 65 uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */ 66 } bit; /*!< Structure used for bit access */ 67 uint16_t reg; /*!< Type used for register access */ 68 } NVMCTRL_CTRLA_Type; 69 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 70 71 #define NVMCTRL_CTRLA_OFFSET 0x00 /**< \brief (NVMCTRL_CTRLA offset) Control A */ 72 #define NVMCTRL_CTRLA_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_CTRLA reset_value) Control A */ 73 74 #define NVMCTRL_CTRLA_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLA) Command */ 75 #define NVMCTRL_CTRLA_CMD_Msk (0x7Ful << NVMCTRL_CTRLA_CMD_Pos) 76 #define NVMCTRL_CTRLA_CMD(value) ((NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos))) 77 #define NVMCTRL_CTRLA_CMD_ER_Val 0x2ul /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */ 78 #define NVMCTRL_CTRLA_CMD_WP_Val 0x4ul /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */ 79 #define NVMCTRL_CTRLA_CMD_EAR_Val 0x5ul /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */ 80 #define NVMCTRL_CTRLA_CMD_WAP_Val 0x6ul /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */ 81 #define NVMCTRL_CTRLA_CMD_SF_Val 0xAul /**< \brief (NVMCTRL_CTRLA) Security Flow Command */ 82 #define NVMCTRL_CTRLA_CMD_WL_Val 0xFul /**< \brief (NVMCTRL_CTRLA) Write lockbits */ 83 #define NVMCTRL_CTRLA_CMD_LR_Val 0x40ul /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */ 84 #define NVMCTRL_CTRLA_CMD_UR_Val 0x41ul /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */ 85 #define NVMCTRL_CTRLA_CMD_SPRM_Val 0x42ul /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */ 86 #define NVMCTRL_CTRLA_CMD_CPRM_Val 0x43ul /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */ 87 #define NVMCTRL_CTRLA_CMD_PBC_Val 0x44ul /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */ 88 #define NVMCTRL_CTRLA_CMD_SSB_Val 0x45ul /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */ 89 #define NVMCTRL_CTRLA_CMD_INVALL_Val 0x46ul /**< \brief (NVMCTRL_CTRLA) Invalidate all cache lines. */ 90 #define NVMCTRL_CTRLA_CMD_ER (NVMCTRL_CTRLA_CMD_ER_Val << NVMCTRL_CTRLA_CMD_Pos) 91 #define NVMCTRL_CTRLA_CMD_WP (NVMCTRL_CTRLA_CMD_WP_Val << NVMCTRL_CTRLA_CMD_Pos) 92 #define NVMCTRL_CTRLA_CMD_EAR (NVMCTRL_CTRLA_CMD_EAR_Val << NVMCTRL_CTRLA_CMD_Pos) 93 #define NVMCTRL_CTRLA_CMD_WAP (NVMCTRL_CTRLA_CMD_WAP_Val << NVMCTRL_CTRLA_CMD_Pos) 94 #define NVMCTRL_CTRLA_CMD_SF (NVMCTRL_CTRLA_CMD_SF_Val << NVMCTRL_CTRLA_CMD_Pos) 95 #define NVMCTRL_CTRLA_CMD_WL (NVMCTRL_CTRLA_CMD_WL_Val << NVMCTRL_CTRLA_CMD_Pos) 96 #define NVMCTRL_CTRLA_CMD_LR (NVMCTRL_CTRLA_CMD_LR_Val << NVMCTRL_CTRLA_CMD_Pos) 97 #define NVMCTRL_CTRLA_CMD_UR (NVMCTRL_CTRLA_CMD_UR_Val << NVMCTRL_CTRLA_CMD_Pos) 98 #define NVMCTRL_CTRLA_CMD_SPRM (NVMCTRL_CTRLA_CMD_SPRM_Val << NVMCTRL_CTRLA_CMD_Pos) 99 #define NVMCTRL_CTRLA_CMD_CPRM (NVMCTRL_CTRLA_CMD_CPRM_Val << NVMCTRL_CTRLA_CMD_Pos) 100 #define NVMCTRL_CTRLA_CMD_PBC (NVMCTRL_CTRLA_CMD_PBC_Val << NVMCTRL_CTRLA_CMD_Pos) 101 #define NVMCTRL_CTRLA_CMD_SSB (NVMCTRL_CTRLA_CMD_SSB_Val << NVMCTRL_CTRLA_CMD_Pos) 102 #define NVMCTRL_CTRLA_CMD_INVALL (NVMCTRL_CTRLA_CMD_INVALL_Val << NVMCTRL_CTRLA_CMD_Pos) 103 #define NVMCTRL_CTRLA_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLA) Command Execution */ 104 #define NVMCTRL_CTRLA_CMDEX_Msk (0xFFul << NVMCTRL_CTRLA_CMDEX_Pos) 105 #define NVMCTRL_CTRLA_CMDEX(value) ((NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos))) 106 #define NVMCTRL_CTRLA_CMDEX_KEY_Val 0xA5ul /**< \brief (NVMCTRL_CTRLA) Execution Key */ 107 #define NVMCTRL_CTRLA_CMDEX_KEY (NVMCTRL_CTRLA_CMDEX_KEY_Val << NVMCTRL_CTRLA_CMDEX_Pos) 108 #define NVMCTRL_CTRLA_MASK 0xFF7Ful /**< \brief (NVMCTRL_CTRLA) MASK Register */ 109 110 /* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */ 111 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 112 typedef union { 113 struct { 114 uint32_t :1; /*!< bit: 0 Reserved */ 115 uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */ 116 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 117 uint32_t MANW:1; /*!< bit: 7 Manual Write */ 118 uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */ 119 uint32_t :6; /*!< bit: 10..15 Reserved */ 120 uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */ 121 uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */ 122 uint32_t :13; /*!< bit: 19..31 Reserved */ 123 } bit; /*!< Structure used for bit access */ 124 uint32_t reg; /*!< Type used for register access */ 125 } NVMCTRL_CTRLB_Type; 126 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 127 128 #define NVMCTRL_CTRLB_OFFSET 0x04 /**< \brief (NVMCTRL_CTRLB offset) Control B */ 129 #define NVMCTRL_CTRLB_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_CTRLB reset_value) Control B */ 130 131 #define NVMCTRL_CTRLB_RWS_Pos 1 /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */ 132 #define NVMCTRL_CTRLB_RWS_Msk (0xFul << NVMCTRL_CTRLB_RWS_Pos) 133 #define NVMCTRL_CTRLB_RWS(value) ((NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos))) 134 #define NVMCTRL_CTRLB_RWS_SINGLE_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */ 135 #define NVMCTRL_CTRLB_RWS_HALF_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */ 136 #define NVMCTRL_CTRLB_RWS_DUAL_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */ 137 #define NVMCTRL_CTRLB_RWS_SINGLE (NVMCTRL_CTRLB_RWS_SINGLE_Val << NVMCTRL_CTRLB_RWS_Pos) 138 #define NVMCTRL_CTRLB_RWS_HALF (NVMCTRL_CTRLB_RWS_HALF_Val << NVMCTRL_CTRLB_RWS_Pos) 139 #define NVMCTRL_CTRLB_RWS_DUAL (NVMCTRL_CTRLB_RWS_DUAL_Val << NVMCTRL_CTRLB_RWS_Pos) 140 #define NVMCTRL_CTRLB_MANW_Pos 7 /**< \brief (NVMCTRL_CTRLB) Manual Write */ 141 #define NVMCTRL_CTRLB_MANW (0x1ul << NVMCTRL_CTRLB_MANW_Pos) 142 #define NVMCTRL_CTRLB_SLEEPPRM_Pos 8 /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */ 143 #define NVMCTRL_CTRLB_SLEEPPRM_Msk (0x3ul << NVMCTRL_CTRLB_SLEEPPRM_Pos) 144 #define NVMCTRL_CTRLB_SLEEPPRM(value) ((NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos))) 145 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */ 146 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */ 147 #define NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3ul /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */ 148 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) 149 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) 150 #define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) 151 #define NVMCTRL_CTRLB_READMODE_Pos 16 /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */ 152 #define NVMCTRL_CTRLB_READMODE_Msk (0x3ul << NVMCTRL_CTRLB_READMODE_Pos) 153 #define NVMCTRL_CTRLB_READMODE(value) ((NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos))) 154 #define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */ 155 #define NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */ 156 #define NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */ 157 #define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos) 158 #define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos) 159 #define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos) 160 #define NVMCTRL_CTRLB_CACHEDIS_Pos 18 /**< \brief (NVMCTRL_CTRLB) Cache Disable */ 161 #define NVMCTRL_CTRLB_CACHEDIS (0x1ul << NVMCTRL_CTRLB_CACHEDIS_Pos) 162 #define NVMCTRL_CTRLB_MASK 0x0007039Eul /**< \brief (NVMCTRL_CTRLB) MASK Register */ 163 164 /* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */ 165 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 166 typedef union { 167 struct { 168 uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */ 169 uint32_t PSZ:3; /*!< bit: 16..18 Page Size */ 170 uint32_t :13; /*!< bit: 19..31 Reserved */ 171 } bit; /*!< Structure used for bit access */ 172 uint32_t reg; /*!< Type used for register access */ 173 } NVMCTRL_PARAM_Type; 174 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 175 176 #define NVMCTRL_PARAM_OFFSET 0x08 /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */ 177 #define NVMCTRL_PARAM_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */ 178 179 #define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */ 180 #define NVMCTRL_PARAM_NVMP_Msk (0xFFFFul << NVMCTRL_PARAM_NVMP_Pos) 181 #define NVMCTRL_PARAM_NVMP(value) ((NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))) 182 #define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */ 183 #define NVMCTRL_PARAM_PSZ_Msk (0x7ul << NVMCTRL_PARAM_PSZ_Pos) 184 #define NVMCTRL_PARAM_PSZ(value) ((NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))) 185 #define NVMCTRL_PARAM_PSZ_8_Val 0x0ul /**< \brief (NVMCTRL_PARAM) 8 bytes */ 186 #define NVMCTRL_PARAM_PSZ_16_Val 0x1ul /**< \brief (NVMCTRL_PARAM) 16 bytes */ 187 #define NVMCTRL_PARAM_PSZ_32_Val 0x2ul /**< \brief (NVMCTRL_PARAM) 32 bytes */ 188 #define NVMCTRL_PARAM_PSZ_64_Val 0x3ul /**< \brief (NVMCTRL_PARAM) 64 bytes */ 189 #define NVMCTRL_PARAM_PSZ_128_Val 0x4ul /**< \brief (NVMCTRL_PARAM) 128 bytes */ 190 #define NVMCTRL_PARAM_PSZ_256_Val 0x5ul /**< \brief (NVMCTRL_PARAM) 256 bytes */ 191 #define NVMCTRL_PARAM_PSZ_512_Val 0x6ul /**< \brief (NVMCTRL_PARAM) 512 bytes */ 192 #define NVMCTRL_PARAM_PSZ_1024_Val 0x7ul /**< \brief (NVMCTRL_PARAM) 1024 bytes */ 193 #define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos) 194 #define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos) 195 #define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos) 196 #define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos) 197 #define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos) 198 #define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos) 199 #define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos) 200 #define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos) 201 #define NVMCTRL_PARAM_MASK 0x0007FFFFul /**< \brief (NVMCTRL_PARAM) MASK Register */ 202 203 /* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */ 204 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 205 typedef union { 206 struct { 207 uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ 208 uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ 209 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 210 } bit; /*!< Structure used for bit access */ 211 uint8_t reg; /*!< Type used for register access */ 212 } NVMCTRL_INTENCLR_Type; 213 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 214 215 #define NVMCTRL_INTENCLR_OFFSET 0x0C /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */ 216 #define NVMCTRL_INTENCLR_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */ 217 218 #define NVMCTRL_INTENCLR_READY_Pos 0 /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */ 219 #define NVMCTRL_INTENCLR_READY (0x1ul << NVMCTRL_INTENCLR_READY_Pos) 220 #define NVMCTRL_INTENCLR_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */ 221 #define NVMCTRL_INTENCLR_ERROR (0x1ul << NVMCTRL_INTENCLR_ERROR_Pos) 222 #define NVMCTRL_INTENCLR_MASK 0x03ul /**< \brief (NVMCTRL_INTENCLR) MASK Register */ 223 224 /* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */ 225 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 226 typedef union { 227 struct { 228 uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ 229 uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ 230 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 231 } bit; /*!< Structure used for bit access */ 232 uint8_t reg; /*!< Type used for register access */ 233 } NVMCTRL_INTENSET_Type; 234 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 235 236 #define NVMCTRL_INTENSET_OFFSET 0x10 /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */ 237 #define NVMCTRL_INTENSET_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */ 238 239 #define NVMCTRL_INTENSET_READY_Pos 0 /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */ 240 #define NVMCTRL_INTENSET_READY (0x1ul << NVMCTRL_INTENSET_READY_Pos) 241 #define NVMCTRL_INTENSET_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */ 242 #define NVMCTRL_INTENSET_ERROR (0x1ul << NVMCTRL_INTENSET_ERROR_Pos) 243 #define NVMCTRL_INTENSET_MASK 0x03ul /**< \brief (NVMCTRL_INTENSET) MASK Register */ 244 245 /* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */ 246 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 247 typedef union { 248 struct { 249 uint8_t READY:1; /*!< bit: 0 NVM Ready */ 250 uint8_t ERROR:1; /*!< bit: 1 Error */ 251 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 252 } bit; /*!< Structure used for bit access */ 253 uint8_t reg; /*!< Type used for register access */ 254 } NVMCTRL_INTFLAG_Type; 255 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 256 257 #define NVMCTRL_INTFLAG_OFFSET 0x14 /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ 258 #define NVMCTRL_INTFLAG_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ 259 260 #define NVMCTRL_INTFLAG_READY_Pos 0 /**< \brief (NVMCTRL_INTFLAG) NVM Ready */ 261 #define NVMCTRL_INTFLAG_READY (0x1ul << NVMCTRL_INTFLAG_READY_Pos) 262 #define NVMCTRL_INTFLAG_ERROR_Pos 1 /**< \brief (NVMCTRL_INTFLAG) Error */ 263 #define NVMCTRL_INTFLAG_ERROR (0x1ul << NVMCTRL_INTFLAG_ERROR_Pos) 264 #define NVMCTRL_INTFLAG_MASK 0x03ul /**< \brief (NVMCTRL_INTFLAG) MASK Register */ 265 266 /* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */ 267 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 268 typedef union { 269 struct { 270 uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */ 271 uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */ 272 uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */ 273 uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */ 274 uint16_t NVME:1; /*!< bit: 4 NVM Error */ 275 uint16_t :3; /*!< bit: 5.. 7 Reserved */ 276 uint16_t SB:1; /*!< bit: 8 Security Bit Status */ 277 uint16_t :7; /*!< bit: 9..15 Reserved */ 278 } bit; /*!< Structure used for bit access */ 279 uint16_t reg; /*!< Type used for register access */ 280 } NVMCTRL_STATUS_Type; 281 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 282 283 #define NVMCTRL_STATUS_OFFSET 0x18 /**< \brief (NVMCTRL_STATUS offset) Status */ 284 #define NVMCTRL_STATUS_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_STATUS reset_value) Status */ 285 286 #define NVMCTRL_STATUS_PRM_Pos 0 /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */ 287 #define NVMCTRL_STATUS_PRM (0x1ul << NVMCTRL_STATUS_PRM_Pos) 288 #define NVMCTRL_STATUS_LOAD_Pos 1 /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */ 289 #define NVMCTRL_STATUS_LOAD (0x1ul << NVMCTRL_STATUS_LOAD_Pos) 290 #define NVMCTRL_STATUS_PROGE_Pos 2 /**< \brief (NVMCTRL_STATUS) Programming Error Status */ 291 #define NVMCTRL_STATUS_PROGE (0x1ul << NVMCTRL_STATUS_PROGE_Pos) 292 #define NVMCTRL_STATUS_LOCKE_Pos 3 /**< \brief (NVMCTRL_STATUS) Lock Error Status */ 293 #define NVMCTRL_STATUS_LOCKE (0x1ul << NVMCTRL_STATUS_LOCKE_Pos) 294 #define NVMCTRL_STATUS_NVME_Pos 4 /**< \brief (NVMCTRL_STATUS) NVM Error */ 295 #define NVMCTRL_STATUS_NVME (0x1ul << NVMCTRL_STATUS_NVME_Pos) 296 #define NVMCTRL_STATUS_SB_Pos 8 /**< \brief (NVMCTRL_STATUS) Security Bit Status */ 297 #define NVMCTRL_STATUS_SB (0x1ul << NVMCTRL_STATUS_SB_Pos) 298 #define NVMCTRL_STATUS_MASK 0x011Ful /**< \brief (NVMCTRL_STATUS) MASK Register */ 299 300 /* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */ 301 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 302 typedef union { 303 struct { 304 uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */ 305 uint32_t :10; /*!< bit: 22..31 Reserved */ 306 } bit; /*!< Structure used for bit access */ 307 uint32_t reg; /*!< Type used for register access */ 308 } NVMCTRL_ADDR_Type; 309 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 310 311 #define NVMCTRL_ADDR_OFFSET 0x1C /**< \brief (NVMCTRL_ADDR offset) Address */ 312 #define NVMCTRL_ADDR_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_ADDR reset_value) Address */ 313 314 #define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */ 315 #define NVMCTRL_ADDR_ADDR_Msk (0x3FFFFFul << NVMCTRL_ADDR_ADDR_Pos) 316 #define NVMCTRL_ADDR_ADDR(value) ((NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))) 317 #define NVMCTRL_ADDR_MASK 0x003FFFFFul /**< \brief (NVMCTRL_ADDR) MASK Register */ 318 319 /* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */ 320 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 321 typedef union { 322 struct { 323 uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */ 324 } bit; /*!< Structure used for bit access */ 325 uint16_t reg; /*!< Type used for register access */ 326 } NVMCTRL_LOCK_Type; 327 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 328 329 #define NVMCTRL_LOCK_OFFSET 0x20 /**< \brief (NVMCTRL_LOCK offset) Lock Section */ 330 #define NVMCTRL_LOCK_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_LOCK reset_value) Lock Section */ 331 332 #define NVMCTRL_LOCK_LOCK_Pos 0 /**< \brief (NVMCTRL_LOCK) Region Lock Bits */ 333 #define NVMCTRL_LOCK_LOCK_Msk (0xFFFFul << NVMCTRL_LOCK_LOCK_Pos) 334 #define NVMCTRL_LOCK_LOCK(value) ((NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos))) 335 #define NVMCTRL_LOCK_MASK 0xFFFFul /**< \brief (NVMCTRL_LOCK) MASK Register */ 336 337 /** \brief NVMCTRL APB hardware registers */ 338 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 339 typedef struct { 340 __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ 341 RoReg8 Reserved1[0x2]; 342 __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */ 343 __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */ 344 __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ 345 RoReg8 Reserved2[0x3]; 346 __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */ 347 RoReg8 Reserved3[0x3]; 348 __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */ 349 RoReg8 Reserved4[0x3]; 350 __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */ 351 RoReg8 Reserved5[0x2]; 352 __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */ 353 __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */ 354 } Nvmctrl; 355 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 356 #define SECTION_NVMCTRL_CAL 357 #define SECTION_NVMCTRL_LOCKBIT 358 #define SECTION_NVMCTRL_OTP1 359 #define SECTION_NVMCTRL_OTP2 360 #define SECTION_NVMCTRL_OTP4 361 #define SECTION_NVMCTRL_TEMP_LOG 362 #define SECTION_NVMCTRL_USER 363 364 /*@}*/ 365 366 /* ************************************************************************** */ 367 /** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */ 368 /* ************************************************************************** */ 369 /** \addtogroup fuses_api Peripheral Software API */ 370 /*@{*/ 371 372 373 #define ADC_FUSES_BIASCAL_ADDR (NVMCTRL_OTP4 + 4) 374 #define ADC_FUSES_BIASCAL_Pos 3 /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */ 375 #define ADC_FUSES_BIASCAL_Msk (0x7ul << ADC_FUSES_BIASCAL_Pos) 376 #define ADC_FUSES_BIASCAL(value) ((ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos))) 377 378 #define ADC_FUSES_LINEARITY_0_ADDR NVMCTRL_OTP4 379 #define ADC_FUSES_LINEARITY_0_Pos 27 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */ 380 #define ADC_FUSES_LINEARITY_0_Msk (0x1Ful << ADC_FUSES_LINEARITY_0_Pos) 381 #define ADC_FUSES_LINEARITY_0(value) ((ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos))) 382 383 #define ADC_FUSES_LINEARITY_1_ADDR (NVMCTRL_OTP4 + 4) 384 #define ADC_FUSES_LINEARITY_1_Pos 0 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */ 385 #define ADC_FUSES_LINEARITY_1_Msk (0x7ul << ADC_FUSES_LINEARITY_1_Pos) 386 #define ADC_FUSES_LINEARITY_1(value) ((ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos))) 387 388 #define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER 389 #define FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */ 390 #define FUSES_BOD33USERLEVEL_Msk (0x3Ful << FUSES_BOD33USERLEVEL_Pos) 391 #define FUSES_BOD33USERLEVEL(value) ((FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))) 392 393 #define FUSES_BOD33_ACTION_ADDR NVMCTRL_USER 394 #define FUSES_BOD33_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BOD33 Action */ 395 #define FUSES_BOD33_ACTION_Msk (0x3ul << FUSES_BOD33_ACTION_Pos) 396 #define FUSES_BOD33_ACTION(value) ((FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))) 397 398 #define FUSES_BOD33_EN_ADDR NVMCTRL_USER 399 #define FUSES_BOD33_EN_Pos 14 /**< \brief (NVMCTRL_USER) BOD33 Enable */ 400 #define FUSES_BOD33_EN_Msk (0x1ul << FUSES_BOD33_EN_Pos) 401 402 #define FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4) 403 #define FUSES_BOD33_HYST_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */ 404 #define FUSES_BOD33_HYST_Msk (0x1ul << FUSES_BOD33_HYST_Pos) 405 406 #define FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4) 407 #define FUSES_DFLL48M_COARSE_CAL_Pos 26 /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */ 408 #define FUSES_DFLL48M_COARSE_CAL_Msk (0x3Ful << FUSES_DFLL48M_COARSE_CAL_Pos) 409 #define FUSES_DFLL48M_COARSE_CAL(value) ((FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos))) 410 411 #define FUSES_DFLL48M_FINE_CAL_ADDR (NVMCTRL_OTP4 + 8) 412 #define FUSES_DFLL48M_FINE_CAL_Pos 0 /**< \brief (NVMCTRL_OTP4) DFLL48M Fine Calibration */ 413 #define FUSES_DFLL48M_FINE_CAL_Msk (0x3FFul << FUSES_DFLL48M_FINE_CAL_Pos) 414 #define FUSES_DFLL48M_FINE_CAL(value) ((FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos))) 415 416 #define FUSES_OSC32KCAL_ADDR (NVMCTRL_OTP4 + 4) 417 #define FUSES_OSC32KCAL_Pos 6 /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */ 418 #define FUSES_OSC32KCAL_Msk (0x7Ful << FUSES_OSC32KCAL_Pos) 419 #define FUSES_OSC32KCAL(value) ((FUSES_OSC32KCAL_Msk & ((value) << FUSES_OSC32KCAL_Pos))) 420 421 #define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER 422 #define NVMCTRL_FUSES_BOOTPROT_Pos 0 /**< \brief (NVMCTRL_USER) Bootloader Size */ 423 #define NVMCTRL_FUSES_BOOTPROT_Msk (0x7ul << NVMCTRL_FUSES_BOOTPROT_Pos) 424 #define NVMCTRL_FUSES_BOOTPROT(value) ((NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))) 425 426 #define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER 427 #define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4 /**< \brief (NVMCTRL_USER) EEPROM Size */ 428 #define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7ul << NVMCTRL_FUSES_EEPROM_SIZE_Pos) 429 #define NVMCTRL_FUSES_EEPROM_SIZE(value) ((NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos))) 430 431 #define NVMCTRL_FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) 432 #define NVMCTRL_FUSES_HOT_ADC_VAL_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */ 433 #define NVMCTRL_FUSES_HOT_ADC_VAL_Msk (0xFFFul << NVMCTRL_FUSES_HOT_ADC_VAL_Pos) 434 #define NVMCTRL_FUSES_HOT_ADC_VAL(value) ((NVMCTRL_FUSES_HOT_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_ADC_VAL_Pos))) 435 436 #define NVMCTRL_FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) 437 #define NVMCTRL_FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */ 438 #define NVMCTRL_FUSES_HOT_INT1V_VAL_Msk (0xFFul << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos) 439 #define NVMCTRL_FUSES_HOT_INT1V_VAL(value) ((NVMCTRL_FUSES_HOT_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos))) 440 441 #define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG 442 #define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */ 443 #define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk (0xFul << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos) 444 #define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos))) 445 446 #define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG 447 #define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */ 448 #define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk (0xFFul << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos) 449 #define NVMCTRL_FUSES_HOT_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos))) 450 451 #define NVMCTRL_FUSES_NVMP_ADDR NVMCTRL_OTP1 452 #define NVMCTRL_FUSES_NVMP_Pos 16 /**< \brief (NVMCTRL_OTP1) Number of NVM Pages */ 453 #define NVMCTRL_FUSES_NVMP_Msk (0xFFFFul << NVMCTRL_FUSES_NVMP_Pos) 454 #define NVMCTRL_FUSES_NVMP(value) ((NVMCTRL_FUSES_NVMP_Msk & ((value) << NVMCTRL_FUSES_NVMP_Pos))) 455 456 #define NVMCTRL_FUSES_NVM_LOCK_ADDR NVMCTRL_OTP1 457 #define NVMCTRL_FUSES_NVM_LOCK_Pos 0 /**< \brief (NVMCTRL_OTP1) NVM Lock */ 458 #define NVMCTRL_FUSES_NVM_LOCK_Msk (0xFFul << NVMCTRL_FUSES_NVM_LOCK_Pos) 459 #define NVMCTRL_FUSES_NVM_LOCK(value) ((NVMCTRL_FUSES_NVM_LOCK_Msk & ((value) << NVMCTRL_FUSES_NVM_LOCK_Pos))) 460 461 #define NVMCTRL_FUSES_PSZ_ADDR NVMCTRL_OTP1 462 #define NVMCTRL_FUSES_PSZ_Pos 8 /**< \brief (NVMCTRL_OTP1) NVM Page Size */ 463 #define NVMCTRL_FUSES_PSZ_Msk (0xFul << NVMCTRL_FUSES_PSZ_Pos) 464 #define NVMCTRL_FUSES_PSZ(value) ((NVMCTRL_FUSES_PSZ_Msk & ((value) << NVMCTRL_FUSES_PSZ_Pos))) 465 466 #define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4) 467 #define NVMCTRL_FUSES_REGION_LOCKS_Pos 16 /**< \brief (NVMCTRL_USER) NVM Region Locks */ 468 #define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFul << NVMCTRL_FUSES_REGION_LOCKS_Pos) 469 #define NVMCTRL_FUSES_REGION_LOCKS(value) ((NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))) 470 471 #define NVMCTRL_FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) 472 #define NVMCTRL_FUSES_ROOM_ADC_VAL_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */ 473 #define NVMCTRL_FUSES_ROOM_ADC_VAL_Msk (0xFFFul << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos) 474 #define NVMCTRL_FUSES_ROOM_ADC_VAL(value) ((NVMCTRL_FUSES_ROOM_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos))) 475 476 #define NVMCTRL_FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG 477 #define NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */ 478 #define NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk (0xFFul << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos) 479 #define NVMCTRL_FUSES_ROOM_INT1V_VAL(value) ((NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos))) 480 481 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG 482 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */ 483 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFul << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos) 484 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos))) 485 486 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG 487 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */ 488 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFul << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos) 489 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos))) 490 491 #define WDT_FUSES_ALWAYSON_ADDR NVMCTRL_USER 492 #define WDT_FUSES_ALWAYSON_Pos 26 /**< \brief (NVMCTRL_USER) WDT Always On */ 493 #define WDT_FUSES_ALWAYSON_Msk (0x1ul << WDT_FUSES_ALWAYSON_Pos) 494 495 #define WDT_FUSES_ENABLE_ADDR NVMCTRL_USER 496 #define WDT_FUSES_ENABLE_Pos 25 /**< \brief (NVMCTRL_USER) WDT Enable */ 497 #define WDT_FUSES_ENABLE_Msk (0x1ul << WDT_FUSES_ENABLE_Pos) 498 499 #define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4) 500 #define WDT_FUSES_EWOFFSET_Pos 3 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */ 501 #define WDT_FUSES_EWOFFSET_Msk (0xFul << WDT_FUSES_EWOFFSET_Pos) 502 #define WDT_FUSES_EWOFFSET(value) ((WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))) 503 504 #define WDT_FUSES_PER_ADDR NVMCTRL_USER 505 #define WDT_FUSES_PER_Pos 27 /**< \brief (NVMCTRL_USER) WDT Period */ 506 #define WDT_FUSES_PER_Msk (0xFul << WDT_FUSES_PER_Pos) 507 #define WDT_FUSES_PER(value) ((WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))) 508 509 #define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4) 510 #define WDT_FUSES_WEN_Pos 7 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */ 511 #define WDT_FUSES_WEN_Msk (0x1ul << WDT_FUSES_WEN_Pos) 512 513 #define WDT_FUSES_WINDOW_0_ADDR NVMCTRL_USER 514 #define WDT_FUSES_WINDOW_0_Pos 31 /**< \brief (NVMCTRL_USER) WDT Window bit 0 */ 515 #define WDT_FUSES_WINDOW_0_Msk (0x1ul << WDT_FUSES_WINDOW_0_Pos) 516 517 #define WDT_FUSES_WINDOW_1_ADDR (NVMCTRL_USER + 4) 518 #define WDT_FUSES_WINDOW_1_Pos 0 /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */ 519 #define WDT_FUSES_WINDOW_1_Msk (0x7ul << WDT_FUSES_WINDOW_1_Pos) 520 #define WDT_FUSES_WINDOW_1(value) ((WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos))) 521 522 /*@}*/ 523 524 #endif /* _SAMD20_NVMCTRL_COMPONENT_ */ 525