1 /** 2 * \file 3 * 4 * \brief Component description for TC 5 * 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 18 * 2. Redistributions in binary form must reproduce the above copyright notice, 19 * this list of conditions and the following disclaimer in the documentation 20 * and/or other materials provided with the distribution. 21 * 22 * 3. The name of Atmel may not be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * 4. This software may only be redistributed and used in connection with an 26 * Atmel microcontroller product. 27 * 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * \asf_license_stop 41 * 42 */ 43 /* 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 45 */ 46 47 #ifndef _SAMD20_TC_COMPONENT_ 48 #define _SAMD20_TC_COMPONENT_ 49 50 /* ========================================================================== */ 51 /** SOFTWARE API DEFINITION FOR TC */ 52 /* ========================================================================== */ 53 /** \addtogroup SAMD20_TC Basic Timer Counter */ 54 /*@{*/ 55 56 #define TC_U2212 57 #define REV_TC 0x112 58 59 /* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */ 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 61 typedef union { 62 struct { 63 uint16_t SWRST:1; /*!< bit: 0 Software Reset */ 64 uint16_t ENABLE:1; /*!< bit: 1 Enable */ 65 uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */ 66 uint16_t :1; /*!< bit: 4 Reserved */ 67 uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */ 68 uint16_t :1; /*!< bit: 7 Reserved */ 69 uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ 70 uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ 71 uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */ 72 uint16_t :2; /*!< bit: 14..15 Reserved */ 73 } bit; /*!< Structure used for bit access */ 74 uint16_t reg; /*!< Type used for register access */ 75 } TC_CTRLA_Type; 76 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 77 78 #define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */ 79 #define TC_CTRLA_RESETVALUE 0x0000ul /**< \brief (TC_CTRLA reset_value) Control A */ 80 81 #define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */ 82 #define TC_CTRLA_SWRST (0x1ul << TC_CTRLA_SWRST_Pos) 83 #define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */ 84 #define TC_CTRLA_ENABLE (0x1ul << TC_CTRLA_ENABLE_Pos) 85 #define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) TC Mode */ 86 #define TC_CTRLA_MODE_Msk (0x3ul << TC_CTRLA_MODE_Pos) 87 #define TC_CTRLA_MODE(value) ((TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))) 88 #define TC_CTRLA_MODE_COUNT16_Val 0x0ul /**< \brief (TC_CTRLA) Counter in 16-bit mode */ 89 #define TC_CTRLA_MODE_COUNT8_Val 0x1ul /**< \brief (TC_CTRLA) Counter in 8-bit mode */ 90 #define TC_CTRLA_MODE_COUNT32_Val 0x2ul /**< \brief (TC_CTRLA) Counter in 32-bit mode */ 91 #define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos) 92 #define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos) 93 #define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos) 94 #define TC_CTRLA_WAVEGEN_Pos 5 /**< \brief (TC_CTRLA) Waveform Generation Operation */ 95 #define TC_CTRLA_WAVEGEN_Msk (0x3ul << TC_CTRLA_WAVEGEN_Pos) 96 #define TC_CTRLA_WAVEGEN(value) ((TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos))) 97 #define TC_CTRLA_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TC_CTRLA) */ 98 #define TC_CTRLA_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TC_CTRLA) */ 99 #define TC_CTRLA_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TC_CTRLA) */ 100 #define TC_CTRLA_WAVEGEN_MPWM_Val 0x3ul /**< \brief (TC_CTRLA) */ 101 #define TC_CTRLA_WAVEGEN_NFRQ (TC_CTRLA_WAVEGEN_NFRQ_Val << TC_CTRLA_WAVEGEN_Pos) 102 #define TC_CTRLA_WAVEGEN_MFRQ (TC_CTRLA_WAVEGEN_MFRQ_Val << TC_CTRLA_WAVEGEN_Pos) 103 #define TC_CTRLA_WAVEGEN_NPWM (TC_CTRLA_WAVEGEN_NPWM_Val << TC_CTRLA_WAVEGEN_Pos) 104 #define TC_CTRLA_WAVEGEN_MPWM (TC_CTRLA_WAVEGEN_MPWM_Val << TC_CTRLA_WAVEGEN_Pos) 105 #define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */ 106 #define TC_CTRLA_PRESCALER_Msk (0x7ul << TC_CTRLA_PRESCALER_Pos) 107 #define TC_CTRLA_PRESCALER(value) ((TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))) 108 #define TC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TC_CTRLA) GCLK_TC */ 109 #define TC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TC_CTRLA) GCLK_TC/2 */ 110 #define TC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TC_CTRLA) GCLK_TC/4 */ 111 #define TC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TC_CTRLA) GCLK_TC/8 */ 112 #define TC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TC_CTRLA) GCLK_TC/16 */ 113 #define TC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TC_CTRLA) GCLK_TC/64 */ 114 #define TC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TC_CTRLA) GCLK_TC/256 */ 115 #define TC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TC_CTRLA) GCLK_TC/1024 */ 116 #define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos) 117 #define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos) 118 #define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos) 119 #define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos) 120 #define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos) 121 #define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos) 122 #define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos) 123 #define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos) 124 #define TC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TC_CTRLA) Run in Standby */ 125 #define TC_CTRLA_RUNSTDBY (0x1ul << TC_CTRLA_RUNSTDBY_Pos) 126 #define TC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */ 127 #define TC_CTRLA_PRESCSYNC_Msk (0x3ul << TC_CTRLA_PRESCSYNC_Pos) 128 #define TC_CTRLA_PRESCSYNC(value) ((TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))) 129 #define TC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TC_CTRLA) Reload or reset Counter on next GCLK */ 130 #define TC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TC_CTRLA) Reload or reset Counter on next prescaler clock */ 131 #define TC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TC_CTRLA) Reload or reset Counter on next GCLK. Reset prescaler counter */ 132 #define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos) 133 #define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos) 134 #define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos) 135 #define TC_CTRLA_MASK 0x3F6Ful /**< \brief (TC_CTRLA) MASK Register */ 136 137 /* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */ 138 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 139 typedef union { 140 struct { 141 uint16_t ADDR:5; /*!< bit: 0.. 4 Address */ 142 uint16_t :9; /*!< bit: 5..13 Reserved */ 143 uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ 144 uint16_t RREQ:1; /*!< bit: 15 Read Request */ 145 } bit; /*!< Structure used for bit access */ 146 uint16_t reg; /*!< Type used for register access */ 147 } TC_READREQ_Type; 148 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 149 150 #define TC_READREQ_OFFSET 0x02 /**< \brief (TC_READREQ offset) Read Request */ 151 #define TC_READREQ_RESETVALUE 0x0000ul /**< \brief (TC_READREQ reset_value) Read Request */ 152 153 #define TC_READREQ_ADDR_Pos 0 /**< \brief (TC_READREQ) Address */ 154 #define TC_READREQ_ADDR_Msk (0x1Ful << TC_READREQ_ADDR_Pos) 155 #define TC_READREQ_ADDR(value) ((TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos))) 156 #define TC_READREQ_RCONT_Pos 14 /**< \brief (TC_READREQ) Read Continuously */ 157 #define TC_READREQ_RCONT (0x1ul << TC_READREQ_RCONT_Pos) 158 #define TC_READREQ_RREQ_Pos 15 /**< \brief (TC_READREQ) Read Request */ 159 #define TC_READREQ_RREQ (0x1ul << TC_READREQ_RREQ_Pos) 160 #define TC_READREQ_MASK 0xC01Ful /**< \brief (TC_READREQ) MASK Register */ 161 162 /* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */ 163 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 164 typedef union { 165 struct { 166 uint8_t DIR:1; /*!< bit: 0 Counter Direction */ 167 uint8_t :1; /*!< bit: 1 Reserved */ 168 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ 169 uint8_t :3; /*!< bit: 3.. 5 Reserved */ 170 uint8_t CMD:2; /*!< bit: 6.. 7 Command */ 171 } bit; /*!< Structure used for bit access */ 172 uint8_t reg; /*!< Type used for register access */ 173 } TC_CTRLBCLR_Type; 174 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 175 176 #define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */ 177 #define TC_CTRLBCLR_RESETVALUE 0x02ul /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */ 178 179 #define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */ 180 #define TC_CTRLBCLR_DIR (0x1ul << TC_CTRLBCLR_DIR_Pos) 181 #define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot */ 182 #define TC_CTRLBCLR_ONESHOT (0x1ul << TC_CTRLBCLR_ONESHOT_Pos) 183 #define TC_CTRLBCLR_CMD_Pos 6 /**< \brief (TC_CTRLBCLR) Command */ 184 #define TC_CTRLBCLR_CMD_Msk (0x3ul << TC_CTRLBCLR_CMD_Pos) 185 #define TC_CTRLBCLR_CMD(value) ((TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))) 186 #define TC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBCLR) No action */ 187 #define TC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBCLR) Force start, restart or retrigger */ 188 #define TC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBCLR) Force stop */ 189 #define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos) 190 #define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos) 191 #define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos) 192 #define TC_CTRLBCLR_MASK 0xC5ul /**< \brief (TC_CTRLBCLR) MASK Register */ 193 194 /* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */ 195 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 196 typedef union { 197 struct { 198 uint8_t DIR:1; /*!< bit: 0 Counter Direction */ 199 uint8_t :1; /*!< bit: 1 Reserved */ 200 uint8_t ONESHOT:1; /*!< bit: 2 One-shot */ 201 uint8_t :3; /*!< bit: 3.. 5 Reserved */ 202 uint8_t CMD:2; /*!< bit: 6.. 7 Command */ 203 } bit; /*!< Structure used for bit access */ 204 uint8_t reg; /*!< Type used for register access */ 205 } TC_CTRLBSET_Type; 206 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 207 208 #define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */ 209 #define TC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TC_CTRLBSET reset_value) Control B Set */ 210 211 #define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */ 212 #define TC_CTRLBSET_DIR (0x1ul << TC_CTRLBSET_DIR_Pos) 213 #define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-shot */ 214 #define TC_CTRLBSET_ONESHOT (0x1ul << TC_CTRLBSET_ONESHOT_Pos) 215 #define TC_CTRLBSET_CMD_Pos 6 /**< \brief (TC_CTRLBSET) Command */ 216 #define TC_CTRLBSET_CMD_Msk (0x3ul << TC_CTRLBSET_CMD_Pos) 217 #define TC_CTRLBSET_CMD(value) ((TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))) 218 #define TC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBSET) No action */ 219 #define TC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBSET) Force start, restart or retrigger */ 220 #define TC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBSET) Force stop */ 221 #define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos) 222 #define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos) 223 #define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos) 224 #define TC_CTRLBSET_MASK 0xC5ul /**< \brief (TC_CTRLBSET) MASK Register */ 225 226 /* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */ 227 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 228 typedef union { 229 struct { 230 uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */ 231 uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */ 232 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 233 uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */ 234 uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */ 235 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 236 } bit; /*!< Structure used for bit access */ 237 struct { 238 uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */ 239 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 240 uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */ 241 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 242 } vec; /*!< Structure used for vec access */ 243 uint8_t reg; /*!< Type used for register access */ 244 } TC_CTRLC_Type; 245 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 246 247 #define TC_CTRLC_OFFSET 0x06 /**< \brief (TC_CTRLC offset) Control C */ 248 #define TC_CTRLC_RESETVALUE 0x00ul /**< \brief (TC_CTRLC reset_value) Control C */ 249 250 #define TC_CTRLC_INVEN0_Pos 0 /**< \brief (TC_CTRLC) Output Waveform 0 Invert Enable */ 251 #define TC_CTRLC_INVEN0 (1 << TC_CTRLC_INVEN0_Pos) 252 #define TC_CTRLC_INVEN1_Pos 1 /**< \brief (TC_CTRLC) Output Waveform 1 Invert Enable */ 253 #define TC_CTRLC_INVEN1 (1 << TC_CTRLC_INVEN1_Pos) 254 #define TC_CTRLC_INVEN_Pos 0 /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */ 255 #define TC_CTRLC_INVEN_Msk (0x3ul << TC_CTRLC_INVEN_Pos) 256 #define TC_CTRLC_INVEN(value) ((TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos))) 257 #define TC_CTRLC_CPTEN0_Pos 4 /**< \brief (TC_CTRLC) Capture Channel 0 Enable */ 258 #define TC_CTRLC_CPTEN0 (1 << TC_CTRLC_CPTEN0_Pos) 259 #define TC_CTRLC_CPTEN1_Pos 5 /**< \brief (TC_CTRLC) Capture Channel 1 Enable */ 260 #define TC_CTRLC_CPTEN1 (1 << TC_CTRLC_CPTEN1_Pos) 261 #define TC_CTRLC_CPTEN_Pos 4 /**< \brief (TC_CTRLC) Capture Channel x Enable */ 262 #define TC_CTRLC_CPTEN_Msk (0x3ul << TC_CTRLC_CPTEN_Pos) 263 #define TC_CTRLC_CPTEN(value) ((TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos))) 264 #define TC_CTRLC_MASK 0x33ul /**< \brief (TC_CTRLC) MASK Register */ 265 266 /* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */ 267 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 268 typedef union { 269 struct { 270 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */ 271 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 272 } bit; /*!< Structure used for bit access */ 273 uint8_t reg; /*!< Type used for register access */ 274 } TC_DBGCTRL_Type; 275 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 276 277 #define TC_DBGCTRL_OFFSET 0x08 /**< \brief (TC_DBGCTRL offset) Debug Control */ 278 #define TC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TC_DBGCTRL reset_value) Debug Control */ 279 280 #define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Debug Run Mode */ 281 #define TC_DBGCTRL_DBGRUN (0x1ul << TC_DBGCTRL_DBGRUN_Pos) 282 #define TC_DBGCTRL_MASK 0x01ul /**< \brief (TC_DBGCTRL) MASK Register */ 283 284 /* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */ 285 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 286 typedef union { 287 struct { 288 uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */ 289 uint16_t :1; /*!< bit: 3 Reserved */ 290 uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */ 291 uint16_t TCEI:1; /*!< bit: 5 TC Event Input */ 292 uint16_t :2; /*!< bit: 6.. 7 Reserved */ 293 uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */ 294 uint16_t :3; /*!< bit: 9..11 Reserved */ 295 uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */ 296 uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */ 297 uint16_t :2; /*!< bit: 14..15 Reserved */ 298 } bit; /*!< Structure used for bit access */ 299 struct { 300 uint16_t :12; /*!< bit: 0..11 Reserved */ 301 uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */ 302 uint16_t :2; /*!< bit: 14..15 Reserved */ 303 } vec; /*!< Structure used for vec access */ 304 uint16_t reg; /*!< Type used for register access */ 305 } TC_EVCTRL_Type; 306 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 307 308 #define TC_EVCTRL_OFFSET 0x0A /**< \brief (TC_EVCTRL offset) Event Control */ 309 #define TC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (TC_EVCTRL reset_value) Event Control */ 310 311 #define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */ 312 #define TC_EVCTRL_EVACT_Msk (0x7ul << TC_EVCTRL_EVACT_Pos) 313 #define TC_EVCTRL_EVACT(value) ((TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))) 314 #define TC_EVCTRL_EVACT_OFF_Val 0x0ul /**< \brief (TC_EVCTRL) Event action disabled */ 315 #define TC_EVCTRL_EVACT_RETRIGGER_Val 0x1ul /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */ 316 #define TC_EVCTRL_EVACT_COUNT_Val 0x2ul /**< \brief (TC_EVCTRL) Count on event */ 317 #define TC_EVCTRL_EVACT_START_Val 0x3ul /**< \brief (TC_EVCTRL) Start TC on event */ 318 #define TC_EVCTRL_EVACT_PPW_Val 0x5ul /**< \brief (TC_EVCTRL) Period captured into CC0 Pulse Width in CC1 */ 319 #define TC_EVCTRL_EVACT_PWP_Val 0x6ul /**< \brief (TC_EVCTRL) Period captured into CC1 Pulse Width on CC0 */ 320 #define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos) 321 #define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos) 322 #define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos) 323 #define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos) 324 #define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos) 325 #define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos) 326 #define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Inverted Event Input */ 327 #define TC_EVCTRL_TCINV (0x1ul << TC_EVCTRL_TCINV_Pos) 328 #define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Input */ 329 #define TC_EVCTRL_TCEI (0x1ul << TC_EVCTRL_TCEI_Pos) 330 #define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Overflow/Underflow Event Output Enable */ 331 #define TC_EVCTRL_OVFEO (0x1ul << TC_EVCTRL_OVFEO_Pos) 332 #define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable */ 333 #define TC_EVCTRL_MCEO0 (1 << TC_EVCTRL_MCEO0_Pos) 334 #define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable */ 335 #define TC_EVCTRL_MCEO1 (1 << TC_EVCTRL_MCEO1_Pos) 336 #define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */ 337 #define TC_EVCTRL_MCEO_Msk (0x3ul << TC_EVCTRL_MCEO_Pos) 338 #define TC_EVCTRL_MCEO(value) ((TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))) 339 #define TC_EVCTRL_MASK 0x3137ul /**< \brief (TC_EVCTRL) MASK Register */ 340 341 /* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */ 342 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 343 typedef union { 344 struct { 345 uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ 346 uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ 347 uint8_t :1; /*!< bit: 2 Reserved */ 348 uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ 349 uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ 350 uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ 351 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 352 } bit; /*!< Structure used for bit access */ 353 struct { 354 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 355 uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ 356 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 357 } vec; /*!< Structure used for vec access */ 358 uint8_t reg; /*!< Type used for register access */ 359 } TC_INTENCLR_Type; 360 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 361 362 #define TC_INTENCLR_OFFSET 0x0C /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */ 363 #define TC_INTENCLR_RESETVALUE 0x00ul /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */ 364 365 #define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) Overflow Interrupt Enable */ 366 #define TC_INTENCLR_OVF (0x1ul << TC_INTENCLR_OVF_Pos) 367 #define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) Error Interrupt Enable */ 368 #define TC_INTENCLR_ERR (0x1ul << TC_INTENCLR_ERR_Pos) 369 #define TC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (TC_INTENCLR) Synchronization Ready Interrupt Enable */ 370 #define TC_INTENCLR_SYNCRDY (0x1ul << TC_INTENCLR_SYNCRDY_Pos) 371 #define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */ 372 #define TC_INTENCLR_MC0 (1 << TC_INTENCLR_MC0_Pos) 373 #define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */ 374 #define TC_INTENCLR_MC1 (1 << TC_INTENCLR_MC1_Pos) 375 #define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */ 376 #define TC_INTENCLR_MC_Msk (0x3ul << TC_INTENCLR_MC_Pos) 377 #define TC_INTENCLR_MC(value) ((TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))) 378 #define TC_INTENCLR_MASK 0x3Bul /**< \brief (TC_INTENCLR) MASK Register */ 379 380 /* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */ 381 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 382 typedef union { 383 struct { 384 uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ 385 uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ 386 uint8_t :1; /*!< bit: 2 Reserved */ 387 uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ 388 uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ 389 uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ 390 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 391 } bit; /*!< Structure used for bit access */ 392 struct { 393 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 394 uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ 395 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 396 } vec; /*!< Structure used for vec access */ 397 uint8_t reg; /*!< Type used for register access */ 398 } TC_INTENSET_Type; 399 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 400 401 #define TC_INTENSET_OFFSET 0x0D /**< \brief (TC_INTENSET offset) Interrupt Enable Set */ 402 #define TC_INTENSET_RESETVALUE 0x00ul /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */ 403 404 #define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) Overflow Interrupt Enable */ 405 #define TC_INTENSET_OVF (0x1ul << TC_INTENSET_OVF_Pos) 406 #define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) Error Interrupt Enable */ 407 #define TC_INTENSET_ERR (0x1ul << TC_INTENSET_ERR_Pos) 408 #define TC_INTENSET_SYNCRDY_Pos 3 /**< \brief (TC_INTENSET) Synchronization Ready Interrupt Enable */ 409 #define TC_INTENSET_SYNCRDY (0x1ul << TC_INTENSET_SYNCRDY_Pos) 410 #define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable */ 411 #define TC_INTENSET_MC0 (1 << TC_INTENSET_MC0_Pos) 412 #define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable */ 413 #define TC_INTENSET_MC1 (1 << TC_INTENSET_MC1_Pos) 414 #define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */ 415 #define TC_INTENSET_MC_Msk (0x3ul << TC_INTENSET_MC_Pos) 416 #define TC_INTENSET_MC(value) ((TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))) 417 #define TC_INTENSET_MASK 0x3Bul /**< \brief (TC_INTENSET) MASK Register */ 418 419 /* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */ 420 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 421 typedef union { 422 struct { 423 uint8_t OVF:1; /*!< bit: 0 Overflow */ 424 uint8_t ERR:1; /*!< bit: 1 Error */ 425 uint8_t :1; /*!< bit: 2 Reserved */ 426 uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ 427 uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */ 428 uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */ 429 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 430 } bit; /*!< Structure used for bit access */ 431 struct { 432 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 433 uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */ 434 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 435 } vec; /*!< Structure used for vec access */ 436 uint8_t reg; /*!< Type used for register access */ 437 } TC_INTFLAG_Type; 438 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 439 440 #define TC_INTFLAG_OFFSET 0x0E /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */ 441 #define TC_INTFLAG_RESETVALUE 0x00ul /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 442 443 #define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) Overflow */ 444 #define TC_INTFLAG_OVF (0x1ul << TC_INTFLAG_OVF_Pos) 445 #define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) Error */ 446 #define TC_INTFLAG_ERR (0x1ul << TC_INTFLAG_ERR_Pos) 447 #define TC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (TC_INTFLAG) Synchronization Ready */ 448 #define TC_INTFLAG_SYNCRDY (0x1ul << TC_INTFLAG_SYNCRDY_Pos) 449 #define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel 0 */ 450 #define TC_INTFLAG_MC0 (1 << TC_INTFLAG_MC0_Pos) 451 #define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) Match or Capture Channel 1 */ 452 #define TC_INTFLAG_MC1 (1 << TC_INTFLAG_MC1_Pos) 453 #define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel x */ 454 #define TC_INTFLAG_MC_Msk (0x3ul << TC_INTFLAG_MC_Pos) 455 #define TC_INTFLAG_MC(value) ((TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))) 456 #define TC_INTFLAG_MASK 0x3Bul /**< \brief (TC_INTFLAG) MASK Register */ 457 458 /* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */ 459 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 460 typedef union { 461 struct { 462 uint8_t :3; /*!< bit: 0.. 2 Reserved */ 463 uint8_t STOP:1; /*!< bit: 3 Stop */ 464 uint8_t SLAVE:1; /*!< bit: 4 Slave */ 465 uint8_t :2; /*!< bit: 5.. 6 Reserved */ 466 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ 467 } bit; /*!< Structure used for bit access */ 468 uint8_t reg; /*!< Type used for register access */ 469 } TC_STATUS_Type; 470 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 471 472 #define TC_STATUS_OFFSET 0x0F /**< \brief (TC_STATUS offset) Status */ 473 #define TC_STATUS_RESETVALUE 0x08ul /**< \brief (TC_STATUS reset_value) Status */ 474 475 #define TC_STATUS_STOP_Pos 3 /**< \brief (TC_STATUS) Stop */ 476 #define TC_STATUS_STOP (0x1ul << TC_STATUS_STOP_Pos) 477 #define TC_STATUS_SLAVE_Pos 4 /**< \brief (TC_STATUS) Slave */ 478 #define TC_STATUS_SLAVE (0x1ul << TC_STATUS_SLAVE_Pos) 479 #define TC_STATUS_SYNCBUSY_Pos 7 /**< \brief (TC_STATUS) Synchronization Busy */ 480 #define TC_STATUS_SYNCBUSY (0x1ul << TC_STATUS_SYNCBUSY_Pos) 481 #define TC_STATUS_MASK 0x98ul /**< \brief (TC_STATUS) MASK Register */ 482 483 /* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */ 484 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 485 typedef union { 486 struct { 487 uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ 488 } bit; /*!< Structure used for bit access */ 489 uint16_t reg; /*!< Type used for register access */ 490 } TC_COUNT16_COUNT_Type; 491 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 492 493 #define TC_COUNT16_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Counter Value */ 494 #define TC_COUNT16_COUNT_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Counter Value */ 495 496 #define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Counter Value */ 497 #define TC_COUNT16_COUNT_COUNT_Msk (0xFFFFul << TC_COUNT16_COUNT_COUNT_Pos) 498 #define TC_COUNT16_COUNT_COUNT(value) ((TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))) 499 #define TC_COUNT16_COUNT_MASK 0xFFFFul /**< \brief (TC_COUNT16_COUNT) MASK Register */ 500 501 /* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */ 502 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 503 typedef union { 504 struct { 505 uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ 506 } bit; /*!< Structure used for bit access */ 507 uint32_t reg; /*!< Type used for register access */ 508 } TC_COUNT32_COUNT_Type; 509 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 510 511 #define TC_COUNT32_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Counter Value */ 512 #define TC_COUNT32_COUNT_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Counter Value */ 513 514 #define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Counter Value */ 515 #define TC_COUNT32_COUNT_COUNT_Msk (0xFFFFFFFFul << TC_COUNT32_COUNT_COUNT_Pos) 516 #define TC_COUNT32_COUNT_COUNT(value) ((TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))) 517 #define TC_COUNT32_COUNT_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_COUNT) MASK Register */ 518 519 /* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */ 520 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 521 typedef union { 522 struct { 523 uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */ 524 } bit; /*!< Structure used for bit access */ 525 uint8_t reg; /*!< Type used for register access */ 526 } TC_COUNT8_COUNT_Type; 527 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 528 529 #define TC_COUNT8_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Counter Value */ 530 #define TC_COUNT8_COUNT_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Counter Value */ 531 532 #define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */ 533 #define TC_COUNT8_COUNT_COUNT_Msk (0xFFul << TC_COUNT8_COUNT_COUNT_Pos) 534 #define TC_COUNT8_COUNT_COUNT(value) ((TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))) 535 #define TC_COUNT8_COUNT_MASK 0xFFul /**< \brief (TC_COUNT8_COUNT) MASK Register */ 536 537 /* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */ 538 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 539 typedef union { 540 struct { 541 uint8_t PER:8; /*!< bit: 0.. 7 Period Value */ 542 } bit; /*!< Structure used for bit access */ 543 uint8_t reg; /*!< Type used for register access */ 544 } TC_COUNT8_PER_Type; 545 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 546 547 #define TC_COUNT8_PER_OFFSET 0x14 /**< \brief (TC_COUNT8_PER offset) COUNT8 Period Value */ 548 #define TC_COUNT8_PER_RESETVALUE 0xFFul /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period Value */ 549 550 #define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */ 551 #define TC_COUNT8_PER_PER_Msk (0xFFul << TC_COUNT8_PER_PER_Pos) 552 #define TC_COUNT8_PER_PER(value) ((TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))) 553 #define TC_COUNT8_PER_MASK 0xFFul /**< \brief (TC_COUNT8_PER) MASK Register */ 554 555 /* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */ 556 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 557 typedef union { 558 struct { 559 uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */ 560 } bit; /*!< Structure used for bit access */ 561 uint16_t reg; /*!< Type used for register access */ 562 } TC_COUNT16_CC_Type; 563 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 564 565 #define TC_COUNT16_CC_OFFSET 0x18 /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare/Capture */ 566 #define TC_COUNT16_CC_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare/Capture */ 567 568 #define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Compare/Capture Value */ 569 #define TC_COUNT16_CC_CC_Msk (0xFFFFul << TC_COUNT16_CC_CC_Pos) 570 #define TC_COUNT16_CC_CC(value) ((TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))) 571 #define TC_COUNT16_CC_MASK 0xFFFFul /**< \brief (TC_COUNT16_CC) MASK Register */ 572 573 /* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */ 574 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 575 typedef union { 576 struct { 577 uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */ 578 } bit; /*!< Structure used for bit access */ 579 uint32_t reg; /*!< Type used for register access */ 580 } TC_COUNT32_CC_Type; 581 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 582 583 #define TC_COUNT32_CC_OFFSET 0x18 /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare/Capture */ 584 #define TC_COUNT32_CC_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare/Capture */ 585 586 #define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Compare/Capture Value */ 587 #define TC_COUNT32_CC_CC_Msk (0xFFFFFFFFul << TC_COUNT32_CC_CC_Pos) 588 #define TC_COUNT32_CC_CC(value) ((TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))) 589 #define TC_COUNT32_CC_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_CC) MASK Register */ 590 591 /* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */ 592 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 593 typedef union { 594 struct { 595 uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */ 596 } bit; /*!< Structure used for bit access */ 597 uint8_t reg; /*!< Type used for register access */ 598 } TC_COUNT8_CC_Type; 599 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 600 601 #define TC_COUNT8_CC_OFFSET 0x18 /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare/Capture */ 602 #define TC_COUNT8_CC_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare/Capture */ 603 604 #define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Compare/Capture Value */ 605 #define TC_COUNT8_CC_CC_Msk (0xFFul << TC_COUNT8_CC_CC_Pos) 606 #define TC_COUNT8_CC_CC(value) ((TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))) 607 #define TC_COUNT8_CC_MASK 0xFFul /**< \brief (TC_COUNT8_CC) MASK Register */ 608 609 /** \brief TC_COUNT8 hardware registers */ 610 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 611 typedef struct { /* 8-bit Counter Mode */ 612 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ 613 __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ 614 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ 615 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ 616 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ 617 RoReg8 Reserved1[0x1]; 618 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ 619 RoReg8 Reserved2[0x1]; 620 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ 621 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ 622 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ 623 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ 624 __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ 625 __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */ 626 RoReg8 Reserved3[0x3]; 627 __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */ 628 RoReg8 Reserved4[0x3]; 629 __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */ 630 } TcCount8; 631 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 632 633 /** \brief TC_COUNT16 hardware registers */ 634 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 635 typedef struct { /* 16-bit Counter Mode */ 636 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ 637 __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ 638 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ 639 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ 640 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ 641 RoReg8 Reserved1[0x1]; 642 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ 643 RoReg8 Reserved2[0x1]; 644 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ 645 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ 646 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ 647 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ 648 __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ 649 __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */ 650 RoReg8 Reserved3[0x6]; 651 __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */ 652 } TcCount16; 653 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 654 655 /** \brief TC_COUNT32 hardware registers */ 656 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 657 typedef struct { /* 32-bit Counter Mode */ 658 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ 659 __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ 660 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ 661 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ 662 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ 663 RoReg8 Reserved1[0x1]; 664 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ 665 RoReg8 Reserved2[0x1]; 666 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ 667 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ 668 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ 669 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ 670 __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ 671 __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */ 672 RoReg8 Reserved3[0x4]; 673 __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */ 674 } TcCount32; 675 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 676 677 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 678 typedef union { 679 TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */ 680 TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */ 681 TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */ 682 } Tc; 683 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 684 685 /*@}*/ 686 687 #endif /* _SAMD20_TC_COMPONENT_ */ 688