1 /** 2 * \file 3 * 4 * \brief Instance description for PM 5 * 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 18 * 2. Redistributions in binary form must reproduce the above copyright notice, 19 * this list of conditions and the following disclaimer in the documentation 20 * and/or other materials provided with the distribution. 21 * 22 * 3. The name of Atmel may not be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * 4. This software may only be redistributed and used in connection with an 26 * Atmel microcontroller product. 27 * 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * \asf_license_stop 41 * 42 */ 43 /* 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 45 */ 46 47 #ifndef _SAMD20_PM_INSTANCE_ 48 #define _SAMD20_PM_INSTANCE_ 49 50 /* ========== Register definition for PM peripheral ========== */ 51 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 52 #define REG_PM_CTRL (0x40000400U) /**< \brief (PM) Control */ 53 #define REG_PM_SLEEP (0x40000401U) /**< \brief (PM) Sleep Mode */ 54 #define REG_PM_CPUSEL (0x40000408U) /**< \brief (PM) CPU Clock Select */ 55 #define REG_PM_APBASEL (0x40000409U) /**< \brief (PM) APBA Clock Select */ 56 #define REG_PM_APBBSEL (0x4000040AU) /**< \brief (PM) APBB Clock Select */ 57 #define REG_PM_APBCSEL (0x4000040BU) /**< \brief (PM) APBC Clock Select */ 58 #define REG_PM_AHBMASK (0x40000414U) /**< \brief (PM) AHB Mask */ 59 #define REG_PM_APBAMASK (0x40000418U) /**< \brief (PM) APBA Mask */ 60 #define REG_PM_APBBMASK (0x4000041CU) /**< \brief (PM) APBB Mask */ 61 #define REG_PM_APBCMASK (0x40000420U) /**< \brief (PM) APBC Mask */ 62 #define REG_PM_INTENCLR (0x40000434U) /**< \brief (PM) Interrupt Enable Clear */ 63 #define REG_PM_INTENSET (0x40000435U) /**< \brief (PM) Interrupt Enable Set */ 64 #define REG_PM_INTFLAG (0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */ 65 #define REG_PM_RCAUSE (0x40000438U) /**< \brief (PM) Reset Cause */ 66 #else 67 #define REG_PM_CTRL (*(RwReg8 *)0x40000400U) /**< \brief (PM) Control */ 68 #define REG_PM_SLEEP (*(RwReg8 *)0x40000401U) /**< \brief (PM) Sleep Mode */ 69 #define REG_PM_CPUSEL (*(RwReg8 *)0x40000408U) /**< \brief (PM) CPU Clock Select */ 70 #define REG_PM_APBASEL (*(RwReg8 *)0x40000409U) /**< \brief (PM) APBA Clock Select */ 71 #define REG_PM_APBBSEL (*(RwReg8 *)0x4000040AU) /**< \brief (PM) APBB Clock Select */ 72 #define REG_PM_APBCSEL (*(RwReg8 *)0x4000040BU) /**< \brief (PM) APBC Clock Select */ 73 #define REG_PM_AHBMASK (*(RwReg *)0x40000414U) /**< \brief (PM) AHB Mask */ 74 #define REG_PM_APBAMASK (*(RwReg *)0x40000418U) /**< \brief (PM) APBA Mask */ 75 #define REG_PM_APBBMASK (*(RwReg *)0x4000041CU) /**< \brief (PM) APBB Mask */ 76 #define REG_PM_APBCMASK (*(RwReg *)0x40000420U) /**< \brief (PM) APBC Mask */ 77 #define REG_PM_INTENCLR (*(RwReg8 *)0x40000434U) /**< \brief (PM) Interrupt Enable Clear */ 78 #define REG_PM_INTENSET (*(RwReg8 *)0x40000435U) /**< \brief (PM) Interrupt Enable Set */ 79 #define REG_PM_INTFLAG (*(RwReg8 *)0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */ 80 #define REG_PM_RCAUSE (*(RoReg8 *)0x40000438U) /**< \brief (PM) Reset Cause */ 81 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 82 83 /* ========== Instance parameters for PM peripheral ========== */ 84 #define PM_CTRL_MCSEL_DFLL48M 3 85 #define PM_CTRL_MCSEL_GCLK 0 86 #define PM_CTRL_MCSEL_OSC8M 1 87 #define PM_CTRL_MCSEL_XOSC 2 88 #define PM_PM_CLK_APB_NUM 2 89 #define PM_SYSTEM_CLOCK 1000000 // System Clock Frequency at Reset 90 91 #endif /* _SAMD20_PM_INSTANCE_ */ 92